component

DRV8353FSRTAR

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by adom

Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs drv8353fsrtar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers drv8353fsrtar: viewers · Ray
drv8353fsrtar-etched.fit.json drv8353fsrtar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
drv8353fsrtar-etched.glb drv8353fsrtar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
drv8353fsrtar-etched.step drv8353fsrtar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
drv8353fsrtar.glb Publish 0.1.0 · Ray
drv8353fsrtar.kicad_mod Publish 0.1.0 · Ray
drv8353fsrtar.kicad_sym Publish 0.1.0 · Ray
drv8353fsrtar.lbr Publish 0.1.0 · Ray
drv8353fsrtar.step Publish 0.1.0 · Ray
package.json drv8353fsrtar: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json drv8353fsrtar: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md Initial commit: component/drv8353fsrtar · Ray

DRV8353FSRTAR

Texas Instruments · Brushless DC (BLDC) Motor Driver · WQFN-40-EP(6x6)

DRV8353FSRTAR from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CPL output Charge pump switch node; connect 47nF external capacitor between CPH and CPL.
2 CPH output Charge pump switch node; connect 47nF external capacitor between CPH and CPL.
3 VM power_in Gate driver power supply input (9-75V recommended); connect 0.1µF bypass and ≥10µF bulk capacitor.
4 VDRAIN input High side MOSFET drain sense input and charge pump reference (7-100V recommended).
5 VCP power_out Charge pump output (≈VDRAIN+10.5V); connect 1µF, 16V filter capacitor to VDRAIN.
6 GHA output High side gate driver output for phase A; connect to high side MOSFET gate.
7 SHA input High side source sense input for phase A; connect to high side MOSFET source.
8 GLA output Low side gate driver output for phase A; connect to low side MOSFET gate.
9 SPA input Low side source sense and shunt amplifier positive input for phase A; connect to MOSFET source and sense resistor high side.
10 SNA input Shunt amplifier negative sense input for phase A; connect to current sense resistor low side.
11 SNB input Shunt amplifier negative sense input for phase B; connect to current sense resistor low side.
12 SPB input Low side source sense and shunt amplifier positive input for phase B; connect to MOSFET source and sense resistor high side.
13 GLB output Low side gate driver output for phase B; connect to low side MOSFET gate.
14 SHB input High side source sense input for phase B; connect to high side MOSFET source.
15 GHB output High side gate driver output for phase B; connect to high side MOSFET gate.
16 GHC output High side gate driver output for phase C; connect to high side MOSFET gate.
17 SHC input High side source sense input for phase C; connect to high side MOSFET source.
18 GLC output Low side gate driver output for phase C; connect to low side MOSFET gate.
19 SPC input Low side source sense and shunt amplifier positive input for phase C; connect to MOSFET source and sense resistor high side.
20 SNC input Shunt amplifier negative sense input for phase C; connect to current sense resistor low side.
21 SOC output Shunt amplifier output for phase C; provides amplified current sense signal.
22 SOB output Shunt amplifier output for phase B; provides amplified current sense signal.
23 SOA output Shunt amplifier output for phase A; provides amplified current sense signal.
24 VREF power_in Shunt amplifier reference voltage input (3-5.5V recommended); connect 0.1µF, 6.3V capacitor to AGND.
25 AGND power_in Device analog ground; connect to system ground for circuit reference.
26 nFAULT tri_state Fault indicator output (open-drain, active low); requires external pull-up resistor to VCC.
27 SDO tri_state Serial data output (open-drain); data shifts out on SCLK rising edge, requires pull-up resistor.
28 SDI input Serial data input; data captured on SCLK falling edge for SPI communication.
29 SCLK input Serial clock input; synchronizes SPI data capture and output timing.
30 nSCS input Serial chip select (active low); logic low enables SPI interface communication.
31 ENABLE input Gate driver enable input; logic low activates low-power sleep mode, 8-40µs pulse resets faults.
32 INHA input High side gate driver control input for phase A; directly controls high side gate output.
33 INLA input Low side gate driver control input for phase A; directly controls low side gate output.
34 INHB input High side gate driver control input for phase B; directly controls high side gate output.
35 INLB input Low side gate driver control input for phase B; directly controls low side gate output.
36 INHC input High side gate driver control input for phase C; directly controls high side gate output.
37 INLC input Low side gate driver control input for phase C; directly controls low side gate output.
38 DVDD power_out 5V internal regulator output (±5% regulated); connect 1µF, 6.3V capacitor to GND (10mA max load).
39 GND power_in Device power ground; connect to system ground for proper circuit operation.
40 VGLS power_out 11V internal regulator output; connect 1µF, 16V capacitor to GND (25mA max, further regulated to 11V at GLx outputs).
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40-EP(6x6)
Category Motor Driver ICs
Pins 41

CAD (KiCad official)

  • Symbol: DRV8353FSRTAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: drv8353fsrtar-etched.step / drv8353fsrtar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8353fsrtar.step / drv8353fsrtar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (83 pp, sha256 e84c59e0a37d8b2f, retrieved 2026-09-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF