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DRV8350FHRTVR

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Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DRV8350FHRTVR

Texas Instruments · Brushless DC (BLDC) Motor Driver · WQFN-32-EP(5x5)

DRV8350FHRTVR from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CPH passive Charge-pump switch node; connect a 47 nF X5R or X7R ceramic capacitor rated for VDRAIN between CPH and CPL.
2 VM power_in Gate-driver supply input, connected to VDRAIN or a separate supply, with a 0.1 µF capacitor rated to VM and at least 10 µF of local bulk capacitance to GND; recommended VM range is 9 to 75 V.
3 VDRAIN input High-side MOSFET drain sense input and charge-pump reference, connected to the common MOSFET drain node; recommended range is 7 to 100 V.
4 VCP power_out Charge-pump output regulated to VDRAIN + 10.5 V, bypassed with a 1 µF 16 V X5R or X7R capacitor between VCP and VDRAIN.
5 GHA output High-side gate driver output for phase A, connected to the high-side power MOSFET gate.
6 SHA input High-side source sense input for phase A, connected to the high-side power MOSFET source.
7 GLA output Low-side gate driver output for phase A, connected to the low-side power MOSFET gate.
8 SLA input Low-side source sense input for phase A, connected to the low-side power MOSFET source.
9 SLB input Low-side source sense input for phase B, connected to the low-side power MOSFET source.
10 GLB output Low-side gate driver output for phase B, connected to the low-side power MOSFET gate.
11 SHB input High-side source sense input for phase B, connected to the high-side power MOSFET source.
12 GHB output High-side gate driver output for phase B, connected to the high-side power MOSFET gate.
13 GHC output High-side gate driver output for phase C, connected to the high-side power MOSFET gate.
14 SHC input High-side source sense input for phase C, connected to the high-side power MOSFET source.
15 GLC output Low-side gate driver output for phase C, connected to the low-side power MOSFET gate.
16 SLC input Low-side source sense input for phase C, connected to the low-side power MOSFET source.
17 nFAULT output Open-drain fault indicator output that is pulled low during a fault and requires an external pull-up resistor; the pull-up voltage is 0 to 5.5 V with up to 5 mA sink current.
18 MODE input PWM input-mode setting, a 4-level input set by an external resistor that selects Independent, 1x PWM, 3x PWM, or 6x PWM mode.
19 IDRIVE input Gate-drive current setting, a 7-level input set by an external resistor that selects 50 to 1000 mA source and 100 to 2000 mA sink strength (or disabled).
20 VDS input VDS overcurrent monitor trip-point setting, a 7-level input set by an external resistor covering 0.06 V to 1 V (or disabled when tied to DVDD).
21 NC unconnected No internal connection; this pin may be left floating or connected to system ground.
22 ENABLE input Gate driver enable; a logic-low level puts the device into low-power sleep mode, and a low pulse of 8 to 40 µs resets fault conditions.
23 INHA input High-side gate driver control input for phase A that controls the high-side gate driver output.
24 INLA input Low-side gate driver control input for phase A that controls the low-side gate driver output.
25 INHB input High-side gate driver control input for phase B that controls the high-side gate driver output.
26 INLB input Low-side gate driver control input for phase B that controls the low-side gate driver output.
27 INHC input High-side gate driver control input for phase C that controls the high-side gate driver output.
28 INLC input Low-side gate driver control input for phase C that controls the low-side gate driver output.
29 DVDD power_out 5 V internal regulator output that can source up to 10 mA externally and is bypassed with a 1 µF 6.3 V X5R or X7R capacitor to GND.
30 GND power_in Primary device ground, connected to the system ground.
31 VGLS power_out 11 V internal regulator output for the low-side gate drivers, bypassed with a 1 µF 16 V X5R or X7R capacitor to GND.
32 CPL passive Charge-pump switch node; connect a 47 nF X5R or X7R ceramic capacitor rated for VDRAIN between CPL and CPH.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-32-EP(5x5)
Category Motor Driver ICs
Pins 33

CAD (KiCad official)

  • Symbol: DRV8350FHRTVR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: drv8350fhrtvr-etched.step / drv8350fhrtvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8350fhrtvr.step / drv8350fhrtvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (83 pp, sha256 e84c59e0a37d8b2f, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF