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DRV8350FHRTVR
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Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+70@@ -0,0 +1,70 @@+# DRV8350FHRTVR++**Texas Instruments** · Brushless DC (BLDC) Motor Driver · WQFN-32-EP(5x5)++DRV8350FHRTVR from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CPH | passive | Charge-pump switch node; connect a 47 nF X5R or X7R ceramic capacitor rated for VDRAIN between CPH and CPL. |+| 2 | VM | power_in | Gate-driver supply input, connected to VDRAIN or a separate supply, with a 0.1 µF capacitor rated to VM and at least 10 µF of local bulk capacitance to GND; recommended VM range is 9 to 75 V. |+| 3 | VDRAIN | input | High-side MOSFET drain sense input and charge-pump reference, connected to the common MOSFET drain node; recommended range is 7 to 100 V. |+| 4 | VCP | power_out | Charge-pump output regulated to VDRAIN + 10.5 V, bypassed with a 1 µF 16 V X5R or X7R capacitor between VCP and VDRAIN. |+| 5 | GHA | output | High-side gate driver output for phase A, connected to the high-side power MOSFET gate. |+| 6 | SHA | input | High-side source sense input for phase A, connected to the high-side power MOSFET source. |+| 7 | GLA | output | Low-side gate driver output for phase A, connected to the low-side power MOSFET gate. |+| 8 | SLA | input | Low-side source sense input for phase A, connected to the low-side power MOSFET source. |+| 9 | SLB | input | Low-side source sense input for phase B, connected to the low-side power MOSFET source. |+| 10 | GLB | output | Low-side gate driver output for phase B, connected to the low-side power MOSFET gate. |+| 11 | SHB | input | High-side source sense input for phase B, connected to the high-side power MOSFET source. |+| 12 | GHB | output | High-side gate driver output for phase B, connected to the high-side power MOSFET gate. |+| 13 | GHC | output | High-side gate driver output for phase C, connected to the high-side power MOSFET gate. |+| 14 | SHC | input | High-side source sense input for phase C, connected to the high-side power MOSFET source. |+| 15 | GLC | output | Low-side gate driver output for phase C, connected to the low-side power MOSFET gate. |+| 16 | SLC | input | Low-side source sense input for phase C, connected to the low-side power MOSFET source. |+| 17 | nFAULT | output | Open-drain fault indicator output that is pulled low during a fault and requires an external pull-up resistor; the pull-up voltage is 0 to 5.5 V with up to 5 mA sink current. |+| 18 | MODE | input | PWM input-mode setting, a 4-level input set by an external resistor that selects Independent, 1x PWM, 3x PWM, or 6x PWM mode. |+| 19 | IDRIVE | input | Gate-drive current setting, a 7-level input set by an external resistor that selects 50 to 1000 mA source and 100 to 2000 mA sink strength (or disabled). |+| 20 | VDS | input | VDS overcurrent monitor trip-point setting, a 7-level input set by an external resistor covering 0.06 V to 1 V (or disabled when tied to DVDD). |+| 21 | NC | unconnected | No internal connection; this pin may be left floating or connected to system ground. |+| 22 | ENABLE | input | Gate driver enable; a logic-low level puts the device into low-power sleep mode, and a low pulse of 8 to 40 µs resets fault conditions. |+| 23 | INHA | input | High-side gate driver control input for phase A that controls the high-side gate driver output. |+| 24 | INLA | input | Low-side gate driver control input for phase A that controls the low-side gate driver output. |+| 25 | INHB | input | High-side gate driver control input for phase B that controls the high-side gate driver output. |+| 26 | INLB | input | Low-side gate driver control input for phase B that controls the low-side gate driver output. |+| 27 | INHC | input | High-side gate driver control input for phase C that controls the high-side gate driver output. |+| 28 | INLC | input | Low-side gate driver control input for phase C that controls the low-side gate driver output. |+| 29 | DVDD | power_out | 5 V internal regulator output that can source up to 10 mA externally and is bypassed with a 1 µF 6.3 V X5R or X7R capacitor to GND. |+| 30 | GND | power_in | Primary device ground, connected to the system ground. |+| 31 | VGLS | power_out | 11 V internal regulator output for the low-side gate drivers, bypassed with a 1 µF 16 V X5R or X7R capacitor to GND. |+| 32 | CPL | passive | Charge-pump switch node; connect a 47 nF X5R or X7R ceramic capacitor rated for VDRAIN between CPL and CPH. |+| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-32-EP(5x5) |+| Category | Motor Driver ICs |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `DRV8350FHRTVR`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `drv8350fhrtvr-etched.step` / `drv8350fhrtvr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8350fhrtvr.step` / `drv8350fhrtvr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8353f) (83 pp, sha256 `e84c59e0a37d8b2f`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8350fhrtvr-datasheet.pdf)
page.jsonadded+350@@ -0,0 +1,350 @@+{+ "slug": "drv8350fhrtvr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "motor driver ics",+ "drv8350fhrtvr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "drv8350fhrtvr.kicad_sym",+ "drv8350fhrtvr.kicad_mod",+ "drv8350fhrtvr.glb",+ "drv8350fhrtvr.step",+ "drv8350fhrtvr.lbr",+ "docs/hero.png",+ "docs/drv8350fhrtvr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "drv8350fhrtvr-hero.glb",+ "drv8350fhrtvr-hero.overlay.json"+ ],+ "component": {+ "mpn": "DRV8350FHRTVR",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-32-EP(5x5)",+ "pin_count": 33,+ "category": "Motor Driver ICs",+ "subcategory": "Brushless DC (BLDC) Motor Driver",+ "datasheet": "https://www.ti.com/cn/lit/gpn/drv8353f",+ "parts": {+ "symbol": "drv8350fhrtvr.kicad_sym",+ "footprint": "drv8350fhrtvr.kicad_mod",+ "model_3d": "drv8350fhrtvr-hero.glb",+ "model_3d_plain": "drv8350fhrtvr.glb",+ "model_3d_step": "drv8350fhrtvr-etched.step",+ "model_3d_step_plain": "drv8350fhrtvr.step",+ "lbr": "drv8350fhrtvr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2868018",+ "digikey": "296-DRV8350FHRTVRTR-ND",+ "mouser": "595-DRV8350FHRTVR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T02:15:18Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-DRV8350FHRTVRTR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-DRV8350FHRTVR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CPH",+ "type": "passive",+ "description": "Charge-pump switch node; connect a 47 nF X5R or X7R ceramic capacitor rated for VDRAIN between CPH and CPL."+ },+ {+ "number": "2",+ "name": "VM",+ "type": "power_in",+ "description": "Gate-driver supply input, connected to VDRAIN or a separate supply, with a 0.1 µF capacitor rated to VM and at least 10 µF of local bulk capacitance to GND; recommended VM range is 9 to 75 V."+ },+ {+ "number": "3",+ "name": "VDRAIN",+ "type": "input",+ "description": "High-side MOSFET drain sense input and charge-pump reference, connected to the common MOSFET drain node; recommended range is 7 to 100 V."+ },+ {+ "number": "4",+ "name": "VCP",+ "type": "power_out",+ "description": "Charge-pump output regulated to VDRAIN + 10.5 V, bypassed with a 1 µF 16 V X5R or X7R capacitor between VCP and VDRAIN."+ },+ {+ "number": "5",+ "name": "GHA",+ "type": "output",+ "description": "High-side gate driver output for phase A, connected to the high-side power MOSFET gate."+ },+ {+ "number": "6",+ "name": "SHA",+ "type": "input",+ "description": "High-side source sense input for phase A, connected to the high-side power MOSFET source."+ },+ {+ "number": "7",+ "name": "GLA",+ "type": "output",+ "description": "Low-side gate driver output for phase A, connected to the low-side power MOSFET gate."+ },+ {+ "number": "8",+ "name": "SLA",+ "type": "input",+ "description": "Low-side source sense input for phase A, connected to the low-side power MOSFET source."+ },+ {+ "number": "9",+ "name": "SLB",+ "type": "input",+ "description": "Low-side source sense input for phase B, connected to the low-side power MOSFET source."+ },+ {+ "number": "10",+ "name": "GLB",+ "type": "output",+ "description": "Low-side gate driver output for phase B, connected to the low-side power MOSFET gate."+ },+ {+ "number": "11",+ "name": "SHB",+ "type": "input",+ "description": "High-side source sense input for phase B, connected to the high-side power MOSFET source."+ },+ {+ "number": "12",+ "name": "GHB",+ "type": "output",+ "description": "High-side gate driver output for phase B, connected to the high-side power MOSFET gate."+ },+ {+ "number": "13",+ "name": "GHC",+ "type": "output",+ "description": "High-side gate driver output for phase C, connected to the high-side power MOSFET gate."+ },+ {+ "number": "14",+ "name": "SHC",+ "type": "input",+ "description": "High-side source sense input for phase C, connected to the high-side power MOSFET source."+ },+ {+ "number": "15",+ "name": "GLC",+ "type": "output",+ "description": "Low-side gate driver output for phase C, connected to the low-side power MOSFET gate."+ },+ {+ "number": "16",+ "name": "SLC",+ "type": "input",+ "description": "Low-side source sense input for phase C, connected to the low-side power MOSFET source."+ },+ {+ "number": "17",+ "name": "nFAULT",+ "type": "output",+ "description": "Open-drain fault indicator output that is pulled low during a fault and requires an external pull-up resistor; the pull-up voltage is 0 to 5.5 V with up to 5 mA sink current."+ },+ {+ "number": "18",+ "name": "MODE",+ "type": "input",+ "description": "PWM input-mode setting, a 4-level input set by an external resistor that selects Independent, 1x PWM, 3x PWM, or 6x PWM mode."+ },+ {+ "number": "19",+ "name": "IDRIVE",+ "type": "input",+ "description": "Gate-drive current setting, a 7-level input set by an external resistor that selects 50 to 1000 mA source and 100 to 2000 mA sink strength (or disabled)."+ },+ {+ "number": "20",+ "name": "VDS",+ "type": "input",+ "description": "VDS overcurrent monitor trip-point setting, a 7-level input set by an external resistor covering 0.06 V to 1 V (or disabled when tied to DVDD)."+ },+ {+ "number": "21",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; this pin may be left floating or connected to system ground."+ },+ {+ "number": "22",+ "name": "ENABLE",+ "type": "input",+ "description": "Gate driver enable; a logic-low level puts the device into low-power sleep mode, and a low pulse of 8 to 40 µs resets fault conditions."+ },+ {+ "number": "23",+ "name": "INHA",+ "type": "input",+ "description": "High-side gate driver control input for phase A that controls the high-side gate driver output."+ },+ {+ "number": "24",+ "name": "INLA",+ "type": "input",+ "description": "Low-side gate driver control input for phase A that controls the low-side gate driver output."+ },+ {+ "number": "25",+ "name": "INHB",+ "type": "input",+ "description": "High-side gate driver control input for phase B that controls the high-side gate driver output."+ },+ {+ "number": "26",+ "name": "INLB",+ "type": "input",+ "description": "Low-side gate driver control input for phase B that controls the low-side gate driver output."+ },+ {+ "number": "27",+ "name": "INHC",+ "type": "input",+ "description": "High-side gate driver control input for phase C that controls the high-side gate driver output."+ },+ {+ "number": "28",+ "name": "INLC",+ "type": "input",+ "description": "Low-side gate driver control input for phase C that controls the low-side gate driver output."+ },+ {+ "number": "29",+ "name": "DVDD",+ "type": "power_out",+ "description": "5 V internal regulator output that can source up to 10 mA externally and is bypassed with a 1 µF 6.3 V X5R or X7R capacitor to GND."+ },+ {+ "number": "30",+ "name": "GND",+ "type": "power_in",+ "description": "Primary device ground, connected to the system ground."+ },+ {+ "number": "31",+ "name": "VGLS",+ "type": "power_out",+ "description": "11 V internal regulator output for the low-side gate drivers, bypassed with a 1 µF 16 V X5R or X7R capacitor to GND."+ },+ {+ "number": "32",+ "name": "CPL",+ "type": "passive",+ "description": "Charge-pump switch node; connect a 47 nF X5R or X7R ceramic capacitor rated for VDRAIN between CPL and CPH."+ },+ {+ "number": "33",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed thermal pad is shown in the package drawing (figure 6-1) but has no printed pin number i; The pin table and figures are in Chinese. Descriptions were translated into English and reduced to o; Datasheet pin types were mapped to KiCad ERC classes. The charge-pump nodes CPH and CPL were marked ",+ "exposed pad 33 added from the footprint"+ ],+ "pages_sent": 52,+ "cost_usd": 0.2728,+ "at": "2026-10-08T02:14:58"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/drv8353f",+ "pages": 83,+ "sha256": "e84c59e0a37d8b2f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "drv8350fhrtvr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.875+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "5fa713ea46b36980895812ed853577889b7cb06d275041a39b99bc0be305dc79",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "drv8350fhrtvr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.875+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "bfe74136efc8d2b372c9f67b706b593308a1400536736ebcff786ff915ff042c",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}