# DRV8323SRTAT

**Texas Instruments** · Brushless DC (BLDC) Motor Driver · WQFN-40-EP(6x6)

DRV8323SRTAT from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CPL | power_in | Charge pump negative switch node; connect 47nF X5R or X7R ceramic capacitor rated at VM between CPH and CPL. |
| 2 | CPH | power_in | Charge pump positive switch node; connect 47nF X5R or X7R ceramic capacitor rated at VM between CPH and CPL. |
| 3 | VCP | power_in | Charge pump output (≈VM + 11V); connect 1µF 25V X5R or X7R capacitor between VCP and VM. |
| 4 | VM | power_in | Gate driver power supply input, 6V to 60V; connect 0.1µF and ≥10µF bulk capacitors to PGND. |
| 5 | VDRAIN | input | High-side MOSFET drain common point input for VDS overvoltage monitor. |
| 6 | GHA | output | High-side gate driver output phase A; supports 1A peak pull current and 2A peak sink current to MOSFET gate. |
| 7 | SHA | bidirectional | High-side source pin phase A; VDS monitor input and gate driver sink current output path from MOSFET source. |
| 8 | GLA | output | Low-side gate driver output phase A; supports 1A peak pull current and 2A peak sink current to MOSFET gate. |
| 9 | SPA | input | Low-side shunt amplifier positive input phase A; connect to low-side MOSFET source and sense resistor high side. |
| 10 | SNA | input | Current sense amplifier negative input phase A; connect to low side of sense resistor or PGND if unused. |
| 11 | SNB | input | Current sense amplifier negative input phase B; connect to low side of sense resistor or PGND if unused. |
| 12 | SPB | input | Low-side shunt amplifier positive input phase B; connect to low-side MOSFET source and sense resistor high side. |
| 13 | GLB | output | Low-side gate driver output phase B; supports 1A peak pull current and 2A peak sink current to MOSFET gate. |
| 14 | SHB | bidirectional | High-side source pin phase B; VDS monitor input and gate driver sink current output path from MOSFET source. |
| 15 | GHB | output | High-side gate driver output phase B; supports 1A peak pull current and 2A peak sink current to MOSFET gate. |
| 16 | GHC | output | High-side gate driver output phase C; supports 1A peak pull current and 2A peak sink current to MOSFET gate. |
| 17 | SHC | bidirectional | High-side source pin phase C; VDS monitor input and gate driver sink current output path from MOSFET source. |
| 18 | GLC | output | Low-side gate driver output phase C; supports 1A peak pull current and 2A peak sink current to MOSFET gate. |
| 19 | SPC | input | Low-side shunt amplifier positive input phase C; connect to low-side MOSFET source and sense resistor high side. |
| 20 | SNC | input | Current sense amplifier negative input phase C; connect to low side of sense resistor or PGND if unused. |
| 21 | SOC | output | Current sense amplifier output phase C; leave open if current sense amplifier not used. |
| 22 | SOB | output | Current sense amplifier output phase B; leave open if current sense amplifier not used. |
| 23 | SOA | output | Current sense amplifier output phase A; leave open if current sense amplifier not used. |
| 24 | VREF | power_in | Current sense amplifier power input and reference (3V to 5.5V); connect 0.1µF 6.3V capacitor to AGND. |
| 25 | nFAULT | tri_state | Fault indicator open-drain output pulled low during fault condition; requires external pull-up resistor. |
| 26 | SDO | tri_state | Serial data output open-drain; shifts out on SCLK rising edge; requires external pull-up resistor. |
| 27 | SDI | input | Serial data input; data captured on SCLK falling edge for SPI register read/write operations. |
| 28 | SCLK | input | Serial clock input; clock signal for SPI communication determining SDI capture and SDO propagation. |
| 29 | nSCS | input | Serial chip select; logic low level enables SPI interface communication with the device. |
| 30 | ENABLE | input | Gate driver enable input; logic low enters low-power sleep mode; 8µs to 40µs pulse clears faults without sleep. |
| 31 | CAL | input | Amplifier calibration input; set logic high to short amplifier inputs and execute automatic offset voltage calibration. |
| 32 | AGND | power_in | Device analog ground connection; must be externally connected to PGND for proper operation. |
| 33 | DVDD | power_in | 3.3V internal regulator output (30mA maximum); connect 1µF 6.3V X5R or X7R capacitor to AGND. |
| 34 | INHA | input | High-side gate driver control input phase A; controls high-side gate driver output in 6x PWM mode. |
| 35 | INLA | input | Low-side gate driver control input phase A; controls low-side gate driver output in 6x PWM mode. |
| 36 | INHB | input | High-side gate driver control input phase B; controls high-side gate driver output in 6x PWM mode. |
| 37 | INLB | input | Low-side gate driver control input phase B; controls low-side gate driver output in 6x PWM mode. |
| 38 | INHC | input | High-side gate driver control input phase C; controls high-side gate driver output in 6x PWM mode. |
| 39 | INLC | input | Low-side gate driver control input phase C; controls low-side gate driver output in 6x PWM mode. |
| 40 | PGND | power_in | Device power ground; serves as low-side gate driver current return path; must be externally connected to AGND. |
| 41 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-40-EP(6x6) |
| Category | Motor Driver ICs |
| Pins | 41 |

## CAD (KiCad official)

- Symbol: `DRV8323SRTAT`
- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`
- 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files: `drv8323srtat-etched.step` / `drv8323srtat-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8323srtat.step` / `drv8323srtat.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8323) (95 pp, sha256 `98e62c0c61f99755`, retrieved 2026-10-01, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/drv8323srtat-datasheet.pdf)