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DRV8323SRTAT
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Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+78@@ -0,0 +1,78 @@+# DRV8323SRTAT++**Texas Instruments** · Brushless DC (BLDC) Motor Driver · WQFN-40-EP(6x6)++DRV8323SRTAT from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CPL | power_in | Charge pump negative switch node; connect 47nF X5R or X7R ceramic capacitor rated at VM between CPH and CPL. |+| 2 | CPH | power_in | Charge pump positive switch node; connect 47nF X5R or X7R ceramic capacitor rated at VM between CPH and CPL. |+| 3 | VCP | power_in | Charge pump output (≈VM + 11V); connect 1µF 25V X5R or X7R capacitor between VCP and VM. |+| 4 | VM | power_in | Gate driver power supply input, 6V to 60V; connect 0.1µF and ≥10µF bulk capacitors to PGND. |+| 5 | VDRAIN | input | High-side MOSFET drain common point input for VDS overvoltage monitor. |+| 6 | GHA | output | High-side gate driver output phase A; supports 1A peak pull current and 2A peak sink current to MOSFET gate. |+| 7 | SHA | bidirectional | High-side source pin phase A; VDS monitor input and gate driver sink current output path from MOSFET source. |+| 8 | GLA | output | Low-side gate driver output phase A; supports 1A peak pull current and 2A peak sink current to MOSFET gate. |+| 9 | SPA | input | Low-side shunt amplifier positive input phase A; connect to low-side MOSFET source and sense resistor high side. |+| 10 | SNA | input | Current sense amplifier negative input phase A; connect to low side of sense resistor or PGND if unused. |+| 11 | SNB | input | Current sense amplifier negative input phase B; connect to low side of sense resistor or PGND if unused. |+| 12 | SPB | input | Low-side shunt amplifier positive input phase B; connect to low-side MOSFET source and sense resistor high side. |+| 13 | GLB | output | Low-side gate driver output phase B; supports 1A peak pull current and 2A peak sink current to MOSFET gate. |+| 14 | SHB | bidirectional | High-side source pin phase B; VDS monitor input and gate driver sink current output path from MOSFET source. |+| 15 | GHB | output | High-side gate driver output phase B; supports 1A peak pull current and 2A peak sink current to MOSFET gate. |+| 16 | GHC | output | High-side gate driver output phase C; supports 1A peak pull current and 2A peak sink current to MOSFET gate. |+| 17 | SHC | bidirectional | High-side source pin phase C; VDS monitor input and gate driver sink current output path from MOSFET source. |+| 18 | GLC | output | Low-side gate driver output phase C; supports 1A peak pull current and 2A peak sink current to MOSFET gate. |+| 19 | SPC | input | Low-side shunt amplifier positive input phase C; connect to low-side MOSFET source and sense resistor high side. |+| 20 | SNC | input | Current sense amplifier negative input phase C; connect to low side of sense resistor or PGND if unused. |+| 21 | SOC | output | Current sense amplifier output phase C; leave open if current sense amplifier not used. |+| 22 | SOB | output | Current sense amplifier output phase B; leave open if current sense amplifier not used. |+| 23 | SOA | output | Current sense amplifier output phase A; leave open if current sense amplifier not used. |+| 24 | VREF | power_in | Current sense amplifier power input and reference (3V to 5.5V); connect 0.1µF 6.3V capacitor to AGND. |+| 25 | nFAULT | tri_state | Fault indicator open-drain output pulled low during fault condition; requires external pull-up resistor. |+| 26 | SDO | tri_state | Serial data output open-drain; shifts out on SCLK rising edge; requires external pull-up resistor. |+| 27 | SDI | input | Serial data input; data captured on SCLK falling edge for SPI register read/write operations. |+| 28 | SCLK | input | Serial clock input; clock signal for SPI communication determining SDI capture and SDO propagation. |+| 29 | nSCS | input | Serial chip select; logic low level enables SPI interface communication with the device. |+| 30 | ENABLE | input | Gate driver enable input; logic low enters low-power sleep mode; 8µs to 40µs pulse clears faults without sleep. |+| 31 | CAL | input | Amplifier calibration input; set logic high to short amplifier inputs and execute automatic offset voltage calibration. |+| 32 | AGND | power_in | Device analog ground connection; must be externally connected to PGND for proper operation. |+| 33 | DVDD | power_in | 3.3V internal regulator output (30mA maximum); connect 1µF 6.3V X5R or X7R capacitor to AGND. |+| 34 | INHA | input | High-side gate driver control input phase A; controls high-side gate driver output in 6x PWM mode. |+| 35 | INLA | input | Low-side gate driver control input phase A; controls low-side gate driver output in 6x PWM mode. |+| 36 | INHB | input | High-side gate driver control input phase B; controls high-side gate driver output in 6x PWM mode. |+| 37 | INLB | input | Low-side gate driver control input phase B; controls low-side gate driver output in 6x PWM mode. |+| 38 | INHC | input | High-side gate driver control input phase C; controls high-side gate driver output in 6x PWM mode. |+| 39 | INLC | input | Low-side gate driver control input phase C; controls low-side gate driver output in 6x PWM mode. |+| 40 | PGND | power_in | Device power ground; serves as low-side gate driver current return path; must be externally connected to AGND. |+| 41 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-40-EP(6x6) |+| Category | Motor Driver ICs |+| Pins | 41 |++## CAD (KiCad official)++- Symbol: `DRV8323SRTAT`+- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`+- 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)+- 3D model files: `drv8323srtat-etched.step` / `drv8323srtat-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8323srtat.step` / `drv8323srtat.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8323) (95 pp, sha256 `98e62c0c61f99755`, retrieved 2026-10-01, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8323srtat-datasheet.pdf)
page.jsonadded+355@@ -0,0 +1,355 @@+{+ "slug": "drv8323srtat",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-40-EP(6x6). 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connect 47nF X5R or X7R ceramic capacitor rated at VM between CPH and CPL."+ },+ {+ "number": "2",+ "name": "CPH",+ "type": "power_in",+ "description": "Charge pump positive switch node; connect 47nF X5R or X7R ceramic capacitor rated at VM between CPH and CPL."+ },+ {+ "number": "3",+ "name": "VCP",+ "type": "power_in",+ "description": "Charge pump output (≈VM + 11V); connect 1µF 25V X5R or X7R capacitor between VCP and VM."+ },+ {+ "number": "4",+ "name": "VM",+ "type": "power_in",+ "description": "Gate driver power supply input, 6V to 60V; connect 0.1µF and ≥10µF bulk capacitors to PGND."+ },+ {+ "number": "5",+ "name": "VDRAIN",+ "type": "input",+ "description": "High-side MOSFET drain common point input for VDS overvoltage monitor."+ },+ {+ "number": "6",+ "name": "GHA",+ "type": "output",+ "description": "High-side gate driver output phase A; supports 1A peak pull current and 2A peak sink current to MOSFET gate."+ },+ {+ "number": "7",+ "name": "SHA",+ "type": "bidirectional",+ "description": "High-side source pin phase A; VDS monitor input and gate driver sink current output path from MOSFET source."+ },+ {+ "number": "8",+ "name": "GLA",+ "type": "output",+ "description": "Low-side gate driver output phase A; supports 1A peak pull current and 2A peak sink current to MOSFET gate."+ },+ {+ "number": "9",+ "name": "SPA",+ "type": "input",+ "description": "Low-side shunt amplifier positive input phase A; connect to low-side MOSFET source and sense resistor high side."+ },+ {+ "number": "10",+ "name": "SNA",+ "type": "input",+ "description": "Current sense amplifier negative input phase A; connect to low side of sense resistor or PGND if unused."+ },+ {+ "number": "11",+ "name": "SNB",+ "type": "input",+ "description": "Current sense amplifier negative input phase B; connect to low side of sense resistor or PGND if unused."+ },+ {+ "number": "12",+ "name": "SPB",+ "type": "input",+ "description": "Low-side shunt amplifier positive input phase B; connect to low-side MOSFET source and sense resistor high side."+ },+ {+ "number": "13",+ "name": "GLB",+ "type": "output",+ "description": "Low-side gate driver output phase B; supports 1A peak pull current and 2A peak sink current to MOSFET gate."+ },+ {+ "number": "14",+ "name": "SHB",+ "type": "bidirectional",+ "description": "High-side source pin phase B; VDS monitor input and gate driver sink current output path from MOSFET source."+ },+ {+ "number": "15",+ "name": "GHB",+ "type": "output",+ "description": "High-side gate driver output phase B; supports 1A peak pull current and 2A peak sink current to MOSFET gate."+ },+ {+ "number": "16",+ "name": "GHC",+ "type": "output",+ "description": "High-side gate driver output phase C; supports 1A peak pull current and 2A peak sink current to MOSFET gate."+ },+ {+ "number": "17",+ "name": "SHC",+ "type": "bidirectional",+ "description": "High-side source pin phase C; VDS monitor input and gate driver sink current output path from MOSFET source."+ },+ {+ "number": "18",+ "name": "GLC",+ "type": "output",+ "description": "Low-side gate driver output phase C; supports 1A peak pull current and 2A peak sink current to MOSFET gate."+ },+ {+ "number": "19",+ "name": "SPC",+ "type": "input",+ "description": "Low-side shunt amplifier positive input phase C; connect to low-side MOSFET source and sense resistor high side."+ },+ {+ "number": "20",+ "name": "SNC",+ "type": "input",+ "description": "Current sense amplifier negative input phase C; connect to low side of sense resistor or PGND if unused."+ },+ {+ "number": "21",+ "name": "SOC",+ "type": "output",+ "description": "Current sense amplifier output phase C; leave open if current sense amplifier not used."+ },+ {+ "number": "22",+ "name": "SOB",+ "type": "output",+ "description": "Current sense amplifier output phase B; leave open if current sense amplifier not used."+ },+ {+ "number": "23",+ "name": "SOA",+ "type": "output",+ "description": "Current sense amplifier output phase A; leave open if current sense amplifier not used."+ },+ {+ "number": "24",+ "name": "VREF",+ "type": "power_in",+ "description": "Current sense amplifier power input and reference (3V to 5.5V); connect 0.1µF 6.3V capacitor to AGND."+ },+ {+ "number": "25",+ "name": "nFAULT",+ "type": "tri_state",+ "description": "Fault indicator open-drain output pulled low during fault condition; requires external pull-up resistor."+ },+ {+ "number": "26",+ "name": "SDO",+ "type": "tri_state",+ "description": "Serial data output open-drain; shifts out on SCLK rising edge; requires external pull-up resistor."+ },+ {+ "number": "27",+ "name": "SDI",+ "type": "input",+ "description": "Serial data input; data captured on SCLK falling edge for SPI register read/write operations."+ },+ {+ "number": "28",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input; clock signal for SPI communication determining SDI capture and SDO propagation."+ },+ {+ "number": "29",+ "name": "nSCS",+ "type": "input",+ "description": "Serial chip select; logic low level enables SPI interface communication with the device."+ },+ {+ "number": "30",+ "name": "ENABLE",+ "type": "input",+ "description": "Gate driver enable input; logic low enters low-power sleep mode; 8µs to 40µs pulse clears faults without sleep."+ },+ {+ "number": "31",+ "name": "CAL",+ "type": "input",+ "description": "Amplifier calibration input; set logic high to short amplifier inputs and execute automatic offset voltage calibration."+ },+ {+ "number": "32",+ "name": "AGND",+ "type": "power_in",+ "description": "Device analog ground connection; must be externally connected to PGND for proper operation."+ },+ {+ "number": "33",+ "name": "DVDD",+ "type": "power_in",+ "description": "3.3V internal regulator output (30mA maximum); connect 1µF 6.3V X5R or X7R capacitor to AGND."+ },+ {+ "number": "34",+ "name": "INHA",+ "type": "input",+ "description": "High-side gate driver control input phase A; controls high-side gate driver output in 6x PWM mode."+ },+ {+ "number": "35",+ "name": "INLA",+ "type": "input",+ "description": "Low-side gate driver control input phase A; controls low-side gate driver output in 6x PWM mode."+ },+ {+ "number": "36",+ "name": "INHB",+ "type": "input",+ "description": "High-side gate driver control input phase B; controls high-side gate driver output in 6x PWM mode."+ },+ {+ "number": "37",+ "name": "INLB",+ "type": "input",+ "description": "Low-side gate driver control input phase B; controls low-side gate driver output in 6x PWM mode."+ },+ {+ "number": "38",+ "name": "INHC",+ "type": "input",+ "description": "High-side gate driver control input phase C; controls high-side gate driver output in 6x PWM mode."+ },+ {+ "number": "39",+ "name": "INLC",+ "type": "input",+ "description": "Low-side gate driver control input phase C; controls low-side gate driver output in 6x PWM mode."+ },+ {+ "number": "40",+ "name": "PGND",+ "type": "power_in",+ "description": "Device power ground; serves as low-side gate driver current return path; must be externally connected to AGND."+ },+ {+ "number": "41",+ "name": "PAD",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 41 added from the footprint"+ ],+ "pages_sent": 57,+ "cost_usd": 0.5124,+ "at": "2026-10-01T00:46:21"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/drv8323",+ "pages": 95,+ "sha256": "98e62c0c61f99755",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}