# DRV8320RHRHAT

**Texas Instruments** · Motor Driver ICs · VQFN-40-EP(6x6)

DRV8320RHRHAT from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Device power ground; connect to system ground. |
| 2 | CPL | passive | Charge pump switching node; connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between CPH and CPL. |
| 3 | CPH | passive | Charge pump switching node; connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between CPH and CPL. |
| 4 | VCP | power_out | Charge pump output; connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between VCP and VM. |
| 5 | VM | power_in | Gate driver power supply input; connect to the bridge power supply with a 0.1-µF VM-rated ceramic capacitor and at least 10-µF local capacitance to PGND. |
| 6 | VDRAIN | input | High-side MOSFET drain sense input; connect to the common point of the MOSFET drains. |
| 7 | GHA | output | High-side gate driver output; connect to the gate of the high-side power MOSFET. |
| 8 | SHA | input | High-side source sense input; connect to the high-side power MOSFET source. |
| 9 | GLA | output | Low-side gate driver output; connect to the gate of the low-side power MOSFET. |
| 10 | SLA | input | Low-side source sense input; connect to the low-side power MOSFET source. |
| 11 | SLB | input | Low-side source sense input; connect to the low-side power MOSFET source. |
| 12 | GLB | output | Low-side gate driver output; connect to the gate of the low-side power MOSFET. |
| 13 | SHB | input | High-side source sense input; connect to the high-side power MOSFET source. |
| 14 | GHB | output | High-side gate driver output; connect to the gate of the high-side power MOSFET. |
| 15 | GHC | output | High-side gate driver output; connect to the gate of the high-side power MOSFET. |
| 16 | SHC | input | High-side source sense input; connect to the high-side power MOSFET source. |
| 17 | GLC | output | Low-side gate driver output; connect to the gate of the low-side power MOSFET. |
| 18 | SLC | input | Low-side source sense input; connect to the low-side power MOSFET source. |
| 19 | GND | power_in | Device ground; connect to system ground. |
| 20 | nFAULT | output | Open-drain fault indicator, pulled logic low during a fault condition and requires an external pullup resistor. |
| 21 | MODE | input | PWM input mode setting; 4-level input set by an external resistor. |
| 22 | IDRIVE | input | Gate drive output current setting; 7-level input set by an external resistor. |
| 23 | VDS | input | VDS monitor trip point setting; 7-level input set by an external resistor. |
| 24 | NC | unconnected | No internal connection; can be left floating or connected to system ground. |
| 25 | ENABLE | input | Gate driver enable; logic low puts the device in low-power sleep mode, and an 8 to 40-µs low pulse resets fault conditions. |
| 26 | AGND | power_in | Device analog ground; connect to system ground. |
| 27 | DVDD | power_out | 3.3-V internal regulator output that can source up to 30 mA externally; connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between DVDD and AGND. |
| 28 | INHA | input | High-side gate driver control input; controls the output of the high-side gate driver. |
| 29 | INLA | input | Low-side gate driver control input; controls the output of the low-side gate driver. |
| 30 | INHB | input | High-side gate driver control input; controls the output of the high-side gate driver. |
| 31 | INLB | input | Low-side gate driver control input; controls the output of the low-side gate driver. |
| 32 | INHC | input | High-side gate driver control input; controls the output of the high-side gate driver. |
| 33 | INLC | input | Low-side gate driver control input; controls the output of the low-side gate driver. |
| 34 | BGND | power_in | Buck regulator ground; connect to system ground. |
| 35 | CB | passive | Buck regulator bootstrap input; connect a X5R or X7R, 0.1-µF, 16-V capacitor between CB and SW. |
| 36 | SW | output | Buck switch node; connect to an inductor, diode, and the CB bootstrap capacitor. |
| 37 | NC | unconnected | No internal connection; can be left floating or connected to system ground. |
| 38 | VIN | power_in | Buck regulator power supply input; place an X5R or X7R, VM-rated ceramic capacitor between VIN and BGND. |
| 39 | nSHDN | input | Buck shutdown input (high voltage tolerant) with internal pullup current source; pull lower than 1.25 V to disable, float to enable. |
| 40 | FB | input | Buck feedback input; a resistor divider from the buck post-inductor output to this pin sets the buck output voltage. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-40-EP(6x6) |
| Category | Power Management ICs |
| Pins | 41 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply voltage (VM) | VVM | 6 |  | 60 | V |  | 12 |
| Buck power supply voltage (VIN) | VVIN | 4 |  | 60 | V |  | 12 |
| Operating ambient temperature | TA | -40 |  | 125 | °C |  | 12 |
| Logic input voltage | VI | 0 |  | 5.5 | V | ENABLE, IDRIVE, INHx, INLx, MODE, VDS | 12 |
| Applied PWM signal | fPWM | 0 |  | 200 | kHz | INHx, INLx | 12 |
| High-side average gate drive current | IGATE_HS | 0 |  | 25 | mA | GHx | 12 |
| Low-side average gate drive current | IGATE_LS | 0 |  | 25 | mA | GLx | 12 |
| External load current (DVDD) | IDVDD | 0 |  | 30 | mA |  | 12 |
| Open drain pullup voltage | VOD | 0 |  | 5.5 | V | nFAULT | 12 |
| Open drain output current | IOD | 0 |  | 5 | mA | nFAULT | 12 |
| Shutdown control input voltage | VnSHDN | 0 |  | 60 | V | nSHDN | 12 |
| Power supply pin voltage (VM) | VM | -0.3 |  | 65 | V |  | 11 |
| MOSFET drain sense pin voltage | VDRAIN | -0.3 |  | 65 | V |  | 11 |
| Charge pump pin voltage (CPH, VCP) |  | -0.3 |  |  | V | max VVM + 13.5 V | 11 |
| DVDD pin voltage |  | -0.3 |  | 3.8 | V |  | 11 |
| Digital pin voltage |  | -0.3 |  | 5.75 | V | ENABLE, IDRIVE, INHx, INLx, MODE, nFAULT, VDS | 11 |
| Buck power supply pin voltage (VIN) | VIN | -0.3 |  | 65 | V |  | 11 |
| Buck feedback pin voltage (FB) | FB | -0.3 |  | 7 | V |  | 11 |
| Bootstrap pin voltage wrt SW (CB) | CB | -0.3 |  | 7 | V |  | 11 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 11 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 11 |
| ESD HBM | V(ESD) | -3000 |  | 3000 | V | Human-body model, ANSI/ESDA/JEDEC JS-001 | 11 |
| ESD CDM | V(ESD) | -1000 |  | 1000 | V | Charged-device model, JESD22-C101 | 11 |
| Junction-to-ambient thermal resistance | RθJA |  | 30.1 |  | °C/W | RHA (VQFN) 40 pins | 12 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 16.7 |  | °C/W | RHA (VQFN) 40 pins | 12 |
| Junction-to-board thermal resistance | RθJB |  | 9.9 |  | °C/W | RHA (VQFN) 40 pins | 12 |
| Junction-to-top characterization parameter | ψJT |  | 0.5 |  | °C/W | RHA (VQFN) 40 pins | 12 |
| Junction-to-board characterization parameter | ψJB |  | 9.9 |  | °C/W | RHA (VQFN) 40 pins | 12 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 2.2 |  | °C/W | RHA (VQFN) 40 pins | 12 |
| VM operating supply current | IVM |  | 10.5 | 14 | mA | VVM = 24 V, ENABLE = 3.3 V, INHx/INLx = 0 V | 13 |
| VM sleep mode supply current (25°C) | IVMQ |  | 12 | 20 | µA | ENABLE = 0 V, VVM = 24 V, TA = 25°C | 13 |
| VM sleep mode supply current (125°C) | IVMQ |  |  | 50 | µA | ENABLE = 0 V, VVM = 24 V, TA = 125°C | 13 |
| Reset pulse time | tRST | 8 |  | 40 | µs | ENABLE = 0 V period to reset faults | 13 |
| Turnon time | tWAKE |  |  | 1 | ms | VVM > VUVLO, ENABLE = 3.3 V to outputs ready | 13 |
| Turnoff time | tSLEEP |  |  | 1 | ms | ENABLE = 0 V to device sleep mode | 13 |
| DVDD regulator voltage | VDVDD | 3 | 3.3 | 3.6 | V | IDVDD = 0 to 30 mA | 13 |
| VCP operating voltage wrt VM (13 V) | VVCP | 8.4 | 11 | 12.5 | V | VVM = 13 V, IVCP = 0 to 25 mA | 13 |
| VCP operating voltage wrt VM (10 V) | VVCP | 6.3 | 9 | 10 | V | VVM = 10 V, IVCP = 0 to 20 mA | 13 |
| VCP operating voltage wrt VM (8 V) | VVCP | 5.4 | 7 | 8 | V | VVM = 8 V, IVCP = 0 to 15 mA | 13 |
| VCP operating voltage wrt VM (6 V) | VVCP | 4 | 5 | 6 | V | VVM = 6 V, IVCP = 0 to 10 mA | 13 |
| Input logic low voltage | VIL | 0 |  | 0.8 | V |  | 13 |
| Input logic high voltage | VIH | 1.5 |  | 5.5 | V |  | 13 |
| Input logic low current | IIL | -5 |  | 5 | µA | VVIN = 0 V | 13 |
| Input logic high current | IIH |  |  | 70 | µA | VVIN = 5 V | 13 |
| Propagation delay | tPD |  |  | 150 | ns | INHx/INLx transition to GHx/GLx transition | 13 |
| Output logic low voltage | VOL |  |  | 0.1 | V | IO = 5 mA | 13 |
| Output high impedance leakage | IOZ | -2 |  | 2 | µA | VO = 5 V | 13 |
| High-side gate drive voltage (13 V) | VGSH | 8.4 | 11 | 12.5 | V | VVM = 13 V, IVCP = 0 to 25 mA | 14 |
| Low-side gate drive voltage (12 V) | VGSL | 9 | 11 | 12 | V | VVM = 12 V, IVGLS = 0 to 25 mA | 14 |
| Low-side gate drive voltage (6 V) | VGSL | 4 | 5 | 6 | V | VVM = 6 V, IVGLS = 0 to 10 mA | 14 |
| VM undervoltage lockout falling | VUVLO | 5.4 | 5.6 | 5.8 | V | VM falling, UVLO report | 16 |
| VM undervoltage lockout rising | VUVLO | 5.6 | 5.8 | 6 | V | VM rising, UVLO recovery | 16 |
| High-side gate clamp positive | VGS_CLAMP | 15 | 16.5 | 18 | V | Positive clamping voltage | 16 |
| Thermal warning temperature | TOTW | 130 | 150 | 165 | °C | Die temperature, TJ | 17 |
| Thermal shutdown temperature | TOTSD | 150 | 170 | 185 | °C | Die temperature, TJ | 17 |
| Buck shutdown supply current | InSHDN |  | 1 | 3 | µA | VnSHDN = 0 V | 17 |
| Rising nSHDN threshold | VnSHDN_TH | 1.05 | 1.25 | 1.38 | V |  | 17 |
| Buck feedback voltage | VFB | 0.747 | 0.765 | 0.782 | V |  | 17 |
| Buck switching frequency | fSW | 595 | 700 | 805 | kHz |  | 17 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | noise into the feedback pin. • Place the input bypass capacitor close to the VIN pin to decrease copper trace resistance which effects the | 71 |

## CAD (KiCad official)

- Symbol: `DRV8320RHRHAT`
- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`
- 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files: `drv8320rhrhat-etched.step` / `drv8320rhrhat-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8320rhrhat.step` / `drv8320rhrhat.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/drv8320rhrhat.pdf) (95 pp, sha256 `70d0198c22d027f4`, retrieved 2026-10-31, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/drv8320rhrhat-datasheet.pdf)