component
DP8810
Public Made by Adomby adom
Shenzhen Developer Microelec MOSFETs, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDP8810
Shenzhen Developer Microelec · MOSFETs · TSSOP-8
DP8810 from Shenzhen Developer Microelec, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D1/D2 | passive | Common drain of MOSFET 1 and MOSFET 2 (dual N-channel, VDS max 20 V, ID 6 A continuous). |
| 2 | S1 | passive | Source of MOSFET 1 (N-channel, VDS max 20 V, ID 6 A continuous). |
| 3 | S1 | passive | Source of MOSFET 1 (N-channel, VDS max 20 V, ID 6 A continuous), tied with pin 2. |
| 4 | G1 | input | Gate of MOSFET 1, ESD protected (2000 V HBM), VGS max ±8 V, threshold 0.55 to 1 V. |
| 5 | G2 | input | Gate of MOSFET 2, ESD protected (2000 V HBM), VGS max ±8 V, threshold 0.55 to 1 V. |
| 6 | S2 | passive | Source of MOSFET 2 (N-channel, VDS max 20 V, ID 6 A continuous). |
| 7 | S2 | passive | Source of MOSFET 2 (N-channel, VDS max 20 V, ID 6 A continuous), tied with pin 6. |
| 8 | D1/D2 | passive | Common drain of MOSFET 1 and MOSFET 2 (dual N-channel, VDS max 20 V), tied with pin 1. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Shenzhen Developer Microelec |
| Package | TSSOP-8 |
| Category | Triode/MOS Tube/Transistor |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | 20 | V | VGS=0V ID=250μA | 3 | ||
| Zero Gate Voltage Drain Current | IDSS | 1 | μA | VDS=16V,VGS=0V | 3 | ||
| Gate-Body Leakage Current | IGSS | -10 | 10 | μA | VGS=±8V,VDS=0V | 3 | |
| Gate Threshold Voltage | VGS(th) | 0.55 | 0.7 | 1 | V | VDS=VGS,ID=250μA | 3 |
| Drain-Source On-State Resistance | RDS(ON) | 14 | 20 | mΩ | VGS=4.5V, ID=6A | 3 | |
| Drain-Source On-State Resistance | RDS(ON) | 17 | 25 | mΩ | VGS=2.5V, ID=5A | 3 | |
| Diode Forward Voltage | VSD | 1.2 | V | VGS=0V,IS=1.7A | 3 | ||
| Drain-Source Diode Forward Current | IS | 2 | A | VGS=0V | 3 | ||
| Drain-Source Voltage | VDS | 20 | V | 2 | |||
| Gate-Source Voltage | VGS | -8 | 8 | V | 2 | ||
| Drain Current-Continuous | ID | 6 | A | @ TJ=25℃ | 2 | ||
| Pulsed Drain Current | IDM | 30 | A | Pulsed | 2 | ||
| Maximum Power Dissipation | PD | 1.5 | W | 2 | |||
| Operating Junction and Storage Temperature Range | TJ,TSTG | -55 | 150 | ℃ | 2 | ||
| Thermal Resistance, Junction-to-Ambient | RθJA | 100 | ℃/W | 2 |
CAD (KiCad official)
- Symbol:
DP8810 - Footprint:
Package_SO:TSSOP-8_3x3mm_P0.65mm - 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
dp8810-etched.step/dp8810-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dp8810.step/dp8810.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Shenzhen Developer Microelec datasheet (8 pp, sha256
8ea98f0f6eb0c96a, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).