DP83TC812SRHARQ1

{
  "slug": "dp83tc812srharq1",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Ethernet Transceivers, VQFN-36(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "interface",
    "dp83tc812srharq1",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
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    "README.md",
    "dp83tc812srharq1.kicad_sym",
    "dp83tc812srharq1.kicad_mod",
    "dp83tc812srharq1.glb",
    "dp83tc812srharq1.step",
    "dp83tc812srharq1.lbr",
    "docs/hero.png",
    "docs/dp83tc812srharq1-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "dp83tc812srharq1-hero.glb",
    "dp83tc812srharq1-hero.overlay.json"
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  "component": {
    "mpn": "DP83TC812SRHARQ1",
    "manufacturer": "Texas Instruments",
    "package": "VQFN-36(6x6)",
    "pin_count": 37,
    "category": "Interface",
    "subcategory": "Ethernet Transceivers",
    "datasheet": "https://www.ti.com/cn/lit/gpn/dp83tc812s-q1",
    "parts": {
      "symbol": "dp83tc812srharq1.kicad_sym",
      "footprint": "dp83tc812srharq1.kicad_mod",
      "model_3d": "dp83tc812srharq1-hero.glb",
      "model_3d_plain": "dp83tc812srharq1.glb",
      "model_3d_step": "dp83tc812srharq1-etched.step",
      "model_3d_step_plain": "dp83tc812srharq1.step",
      "lbr": "dp83tc812srharq1.lbr"
    },
    "distributor_links": {
      "lcsc": "C3225813",
      "digikey": "296-DP83TC812SRHARQ1TR-ND",
      "mouser": "595-DP83TC812SRHARQ1"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T00:05:43Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-DP83TC812SRHARQ1TR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-DP83TC812SRHARQ1",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "MDC",
        "type": "input",
        "description": "Management data clock for the serial management interface (MDIO is clocked on its rising edge), with a maximum rate of 20 MHz and no minimum rate; it may be asynchronous to the MAC clocks."
      },
      {
        "number": "2",
        "name": "INT_N",
        "type": "bidirectional",
        "description": "Active-low interrupt output (open-drain with a weak internal pull-up of about 9 kΩ) that can be reconfigured to active-high via register 0x0011 and can also serve as a power-down control input."
      },
      {
        "number": "3",
        "name": "RESET_N",
        "type": "input",
        "description": "Active-low reset input with an internal pull-up of about 9 kΩ; a low pulse of at least 1 µs forces a reset, and the strap pins are resampled when it is released."
      },
      {
        "number": "4",
        "name": "XO",
        "type": "output",
        "description": "Crystal-only reference clock output that must be left unconnected when a CMOS-level oscillator is driven into XI."
      },
      {
        "number": "5",
        "name": "XI",
        "type": "input",
        "description": "Reference clock input for a 25 MHz crystal or oscillator (50 MHz oscillator in RMII slave mode), with a 100 Ω series resistor recommended when a crystal is used."
      },
      {
        "number": "6",
        "name": "LED_1/GPIO_1",
        "type": "bidirectional",
        "description": "Link-status LED that blinks on TX/RX activity, in the VDDIO domain, which can alternatively be configured as a clock output or GPIO by strap or register."
      },
      {
        "number": "7",
        "name": "VSLEEP",
        "type": "power_in",
        "description": "TC-10 sleep supply that must be 3.3 V (2.97 V to 3.63 V) and should be decoupled with a 0.1 µF ceramic capacitor."
      },
      {
        "number": "8",
        "name": "WAKE",
        "type": "bidirectional",
        "description": "Wake input (default active-high) that brings the PHY out of TC-10 sleep, which in the VSLEEP domain also drives 40 µs wake-forwarding pulses and may use an optional 10 kΩ pull-down to prevent accidental wake."
      },
      {
        "number": "9",
        "name": "PIN_9",
        "type": "unconnected",
        "description": "Not connected on the DP83TC812 package; the datasheet recommends connecting it to pin 21 for DP83TC815 adaptation."
      },
      {
        "number": "10",
        "name": "INH",
        "type": "bidirectional",
        "description": "High-active open-drain output that is Hi-Z in TC-10 sleep and high in all other states, requiring an external 2 kΩ to 10 kΩ pull-down when used in a TC-10 circuit (one pull-down if shared)."
      },
      {
        "number": "11",
        "name": "VDDA",
        "type": "power_in",
        "description": "3.3 V core supply (2.97 V to 3.63 V) that should be decoupled with 0.47 µF and 0.01 µF ceramic capacitors, with an optional ferrite bead."
      },
      {
        "number": "12",
        "name": "TRD_P",
        "type": "bidirectional",
        "description": "Positive side of the 100BASE-T1 differential media pair (IEEE 802.3bw) with ±8 kV HBM and IEC 61000-4-2 contact-discharge ESD rating."
      },
      {
        "number": "13",
        "name": "TRD_M",
        "type": "bidirectional",
        "description": "Negative side of the 100BASE-T1 differential media pair (IEEE 802.3bw) with ±8 kV HBM and IEC 61000-4-2 contact-discharge ESD rating."
      },
      {
        "number": "14",
        "name": "RX_ER",
        "type": "output",
        "description": "Receive error output in MII and RMII modes, synchronous to RX_CLK or the reference clock rising edge, unused in RGMII and SGMII modes, and also a 3-level PHY address strap."
      },
      {
        "number": "15",
        "name": "RX_DV/CRS_DV/RX_CTRL",
        "type": "output",
        "description": "Receive data valid in MII, carrier-sense/data-valid in RMII (default CRS_DV, selectable via register 0x0551), and RGMII receive control; also a 3-level PHY address strap."
      },
      {
        "number": "16",
        "name": "CLKOUT/GPIO_2",
        "type": "bidirectional",
        "description": "25 MHz reference clock output (50 MHz in RMII slave mode) that can alternatively be configured as an LED or GPIO by strap or register."
      },
      {
        "number": "17",
        "name": "GND_ESC",
        "type": "power_in",
        "description": "Optional ground-escape pin that may be tied to ground for PCB layout or left open, and that does not replace the DAP power-ground connection."
      },
      {
        "number": "18",
        "name": "GND_ESC",
        "type": "power_in",
        "description": "Optional ground-escape pin that may be tied to ground for PCB layout or left open, and that does not replace the DAP power-ground connection."
      },
      {
        "number": "19",
        "name": "DNC",
        "type": "unconnected",
        "description": "Do not connect; leave floating."
      },
      {
        "number": "20",
        "name": "DNC",
        "type": "unconnected",
        "description": "Do not connect; leave floating."
      },
      {
        "number": "21",
        "name": "PIN_21",
        "type": "passive",
        "description": "For DP83TC815 adaptation, 2.2 µF and 0.1 µF ceramic capacitors are connected from this pin to GND."
      },
      {
        "number": "22",
        "name": "VDDMAC",
        "type": "power_in",
        "description": "Optional separate MAC-interface supply of 1.8 V, 2.5 V or 3.3 V that must be tied to VDDIO when not used and should be decoupled with 0.47 µF and 0.01 µF capacitors plus a ferrite bead."
      },
      {
        "number": "23",
        "name": "RX_D3/RX_M",
        "type": "output",
        "description": "MAC receive data bit 3 (MII and RGMII) that outputs a 50 MHz clock in RMII master mode and serves as the SGMII RX_M differential output, with its strap resistor also setting the CLKOUT pin."
      },
      {
        "number": "24",
        "name": "RX_D2/RX_P",
        "type": "output",
        "description": "MAC receive data bit 2 (MII and RGMII) that is not used in RMII slave mode and serves as the SGMII RX_P differential output."
      },
      {
        "number": "25",
        "name": "RX_D1",
        "type": "output",
        "description": "MAC receive data bit 1 that carries RMII receive data bit 1 in RMII mode, is driven from the VDDMAC domain, and is one of the MAC interface data outputs."
      },
      {
        "number": "26",
        "name": "RX_D0",
        "type": "output",
        "description": "MAC receive data bit 0 that carries RMII receive data bit 0 in RMII mode, is driven from the VDDMAC domain, and is one of the MAC interface data outputs."
      },
      {
        "number": "27",
        "name": "RX_CLK",
        "type": "output",
        "description": "25 MHz receive clock in MII and RGMII modes, which is unused in RMII and SGMII modes."
      },
      {
        "number": "28",
        "name": "TX_CLK",
        "type": "bidirectional",
        "description": "25 MHz output (50 Ω driver) in MII mode and clock input from the MAC in RGMII mode, which is unused in RMII and SGMII modes."
      },
      {
        "number": "29",
        "name": "TX_EN/TX_CTRL",
        "type": "input",
        "description": "Transmit enable in MII and RMII modes, and transmit control in RGMII mode, which must be valid before the transmit clock rising edge; unused in SGMII mode."
      },
      {
        "number": "30",
        "name": "TX_D3",
        "type": "input",
        "description": "MAC transmit data bit 3 (MII and RGMII) latched before the TX_CLK rising edge, which is unused in RMII slave mode for TX_D[3:2]."
      },
      {
        "number": "31",
        "name": "TX_D2",
        "type": "input",
        "description": "MAC transmit data bit 2 (MII and RGMII) latched before the TX_CLK rising edge, which is unused in RMII slave mode."
      },
      {
        "number": "32",
        "name": "TX_D1/TX_P",
        "type": "input",
        "description": "MAC transmit data bit 1 (MII, RGMII, and RMII TX_D[1:0]) that serves as the SGMII TX_P differential data input."
      },
      {
        "number": "33",
        "name": "TX_D0/TX_M",
        "type": "input",
        "description": "MAC transmit data bit 0 (MII, RGMII, and RMII TX_D[1:0]) that serves as the SGMII TX_M differential data input."
      },
      {
        "number": "34",
        "name": "VDDIO",
        "type": "power_in",
        "description": "I/O supply of 1.8 V, 2.5 V or 3.3 V that should be decoupled with a ferrite bead, 0.47 µF and 0.01 µF ceramic capacitors."
      },
      {
        "number": "35",
        "name": "LED_0/GPIO_0",
        "type": "bidirectional",
        "description": "Link-status LED that can alternatively be configured as a clock output or GPIO, and whose internal pull-down defaults the device to 100BASE-T1 slave mode unless an external pull-up is added."
      },
      {
        "number": "36",
        "name": "MDIO",
        "type": "bidirectional",
        "description": "Open-drain management data input/output that requires a pull-up to VDDIO of 2.2 kΩ to 9 kΩ and is needed for Open Alliance compliance testing."
      },
      {
        "number": "37",
        "name": "GND",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The MPN DP83TC812SRHARQ1 is the S variant (SGMII supported) in the 36-pin RHA VQFN, confirmed by the; The exposed thermal pad (DAP) is a required ground connection that is not a numbered pin, so it is o; Pins 9 and 21 are labelled PIN_9 and PIN_21 in the figures, with the table listing them as NC/float.",
          "exposed pad 37 added from the footprint",
          "2/37 pins cited to the wrong page (name found elsewhere): ['9:PIN_9@p8', '21:PIN_21@p8']"
        ],
        "pages_sent": 90,
        "cost_usd": 0.4062,
        "at": "2026-10-08T00:05:20"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/dp83tc812s-q1",
        "pages": 181,
        "sha256": "a3e7d5c238ec4704",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 37,
        "described": 37,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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    "models_3d": [
      {
        "file": "dp83tc812srharq1.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          6.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "6212c4fd2463ccb7c6ae2c35f5e24c80884153fcaeaf8e86549c0e49087bc8bb",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "dp83tc812srharq1-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "2080b8e36690e19f6643a5bc975c52bfcf17261adde95dac5960f504f7c33624",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
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  }
}