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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83TC812SRHARQ1

Texas Instruments · Ethernet Transceivers · VQFN-36(6x6)

DP83TC812SRHARQ1 from Texas Instruments, in a VQFN-36(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MDC	input	Management data clock for the serial management interface (MDIO is clocked on its rising edge), with a maximum rate of 20 MHz and no minimum rate; it may be asynchronous to the MAC clocks.
2	INT_N	bidirectional	Active-low interrupt output (open-drain with a weak internal pull-up of about 9 kΩ) that can be reconfigured to active-high via register 0x0011 and can also serve as a power-down control input.
3	RESET_N	input	Active-low reset input with an internal pull-up of about 9 kΩ; a low pulse of at least 1 µs forces a reset, and the strap pins are resampled when it is released.
4	XO	output	Crystal-only reference clock output that must be left unconnected when a CMOS-level oscillator is driven into XI.
5	XI	input	Reference clock input for a 25 MHz crystal or oscillator (50 MHz oscillator in RMII slave mode), with a 100 Ω series resistor recommended when a crystal is used.
6	LED_1/GPIO_1	bidirectional	Link-status LED that blinks on TX/RX activity, in the VDDIO domain, which can alternatively be configured as a clock output or GPIO by strap or register.
7	VSLEEP	power_in	TC-10 sleep supply that must be 3.3 V (2.97 V to 3.63 V) and should be decoupled with a 0.1 µF ceramic capacitor.
8	WAKE	bidirectional	Wake input (default active-high) that brings the PHY out of TC-10 sleep, which in the VSLEEP domain also drives 40 µs wake-forwarding pulses and may use an optional 10 kΩ pull-down to prevent accidental wake.
9	PIN_9	unconnected	Not connected on the DP83TC812 package; the datasheet recommends connecting it to pin 21 for DP83TC815 adaptation.
10	INH	bidirectional	High-active open-drain output that is Hi-Z in TC-10 sleep and high in all other states, requiring an external 2 kΩ to 10 kΩ pull-down when used in a TC-10 circuit (one pull-down if shared).
11	VDDA	power_in	3.3 V core supply (2.97 V to 3.63 V) that should be decoupled with 0.47 µF and 0.01 µF ceramic capacitors, with an optional ferrite bead.
12	TRD_P	bidirectional	Positive side of the 100BASE-T1 differential media pair (IEEE 802.3bw) with ±8 kV HBM and IEC 61000-4-2 contact-discharge ESD rating.
13	TRD_M	bidirectional	Negative side of the 100BASE-T1 differential media pair (IEEE 802.3bw) with ±8 kV HBM and IEC 61000-4-2 contact-discharge ESD rating.
14	RX_ER	output	Receive error output in MII and RMII modes, synchronous to RX_CLK or the reference clock rising edge, unused in RGMII and SGMII modes, and also a 3-level PHY address strap.
15	RX_DV/CRS_DV/RX_CTRL	output	Receive data valid in MII, carrier-sense/data-valid in RMII (default CRS_DV, selectable via register 0x0551), and RGMII receive control; also a 3-level PHY address strap.
16	CLKOUT/GPIO_2	bidirectional	25 MHz reference clock output (50 MHz in RMII slave mode) that can alternatively be configured as an LED or GPIO by strap or register.
17	GND_ESC	power_in	Optional ground-escape pin that may be tied to ground for PCB layout or left open, and that does not replace the DAP power-ground connection.
18	GND_ESC	power_in	Optional ground-escape pin that may be tied to ground for PCB layout or left open, and that does not replace the DAP power-ground connection.
19	DNC	unconnected	Do not connect; leave floating.
20	DNC	unconnected	Do not connect; leave floating.
21	PIN_21	passive	For DP83TC815 adaptation, 2.2 µF and 0.1 µF ceramic capacitors are connected from this pin to GND.
22	VDDMAC	power_in	Optional separate MAC-interface supply of 1.8 V, 2.5 V or 3.3 V that must be tied to VDDIO when not used and should be decoupled with 0.47 µF and 0.01 µF capacitors plus a ferrite bead.
23	RX_D3/RX_M	output	MAC receive data bit 3 (MII and RGMII) that outputs a 50 MHz clock in RMII master mode and serves as the SGMII RX_M differential output, with its strap resistor also setting the CLKOUT pin.
24	RX_D2/RX_P	output	MAC receive data bit 2 (MII and RGMII) that is not used in RMII slave mode and serves as the SGMII RX_P differential output.
25	RX_D1	output	MAC receive data bit 1 that carries RMII receive data bit 1 in RMII mode, is driven from the VDDMAC domain, and is one of the MAC interface data outputs.
26	RX_D0	output	MAC receive data bit 0 that carries RMII receive data bit 0 in RMII mode, is driven from the VDDMAC domain, and is one of the MAC interface data outputs.
27	RX_CLK	output	25 MHz receive clock in MII and RGMII modes, which is unused in RMII and SGMII modes.
28	TX_CLK	bidirectional	25 MHz output (50 Ω driver) in MII mode and clock input from the MAC in RGMII mode, which is unused in RMII and SGMII modes.
29	TX_EN/TX_CTRL	input	Transmit enable in MII and RMII modes, and transmit control in RGMII mode, which must be valid before the transmit clock rising edge; unused in SGMII mode.
30	TX_D3	input	MAC transmit data bit 3 (MII and RGMII) latched before the TX_CLK rising edge, which is unused in RMII slave mode for TX_D[3:2].
31	TX_D2	input	MAC transmit data bit 2 (MII and RGMII) latched before the TX_CLK rising edge, which is unused in RMII slave mode.
32	TX_D1/TX_P	input	MAC transmit data bit 1 (MII, RGMII, and RMII TX_D[1:0]) that serves as the SGMII TX_P differential data input.
33	TX_D0/TX_M	input	MAC transmit data bit 0 (MII, RGMII, and RMII TX_D[1:0]) that serves as the SGMII TX_M differential data input.
34	VDDIO	power_in	I/O supply of 1.8 V, 2.5 V or 3.3 V that should be decoupled with a ferrite bead, 0.47 µF and 0.01 µF ceramic capacitors.
35	LED_0/GPIO_0	bidirectional	Link-status LED that can alternatively be configured as a clock output or GPIO, and whose internal pull-down defaults the device to 100BASE-T1 slave mode unless an external pull-up is added.
36	MDIO	bidirectional	Open-drain management data input/output that requires a pull-up to VDDIO of 2.2 kΩ to 9 kΩ and is needed for Open Alliance compliance testing.
37	GND	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-36(6x6)
Category	Interface
Pins	37

CAD (KiCad official)

Symbol: DP83TC812SRHARQ1
Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
3D model: VQFN-36(6x6) (KiCad packages3D, STEP)
3D model files: dp83tc812srharq1-etched.step / dp83tc812srharq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83tc812srharq1.step / dp83tc812srharq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (181 pp, sha256 a3e7d5c238ec4704, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF