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DP83869HMRGZR

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Texas Instruments Ethernet Transceivers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DP83869HMRGZR

Texas Instruments · Ethernet Transceivers · VQFN-48-EP(7x7)

DP83869HMRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TD_P_A bidirectional Differential transmit and receive signal (pair P) for 1000Base-T channel A, 100Ω differential impedance.
2 TD_M_A bidirectional Differential transmit and receive signal (pair M) for 1000Base-T channel A, 100Ω differential impedance.
3 VDDA2P5 power_in 2.5V analog power supply ±5%; requires 1µF and 0.1µF decoupling capacitors to ground.
4 TD_P_B bidirectional Differential transmit and receive signal (pair P) for 1000Base-T channel B, 100Ω differential impedance.
5 TD_M_B bidirectional Differential transmit and receive signal (pair M) for 1000Base-T channel B, 100Ω differential impedance.
6 VDD1P1 power_in 1.1V digital power supply ±10%; requires 1µF and 0.1µF decoupling capacitors to ground.
7 TD_P_C bidirectional Differential transmit and receive signal (pair P) for 1000Base-T channel C, 100Ω differential impedance.
8 TD_M_C bidirectional Differential transmit and receive signal (pair M) for 1000Base-T channel C, 100Ω differential impedance.
9 VDDA2P5 power_in 2.5V analog power supply ±5%; requires 1µF and 0.1µF decoupling capacitors to ground.
10 TD_P_D bidirectional Differential transmit and receive signal (pair P) for 1000Base-T channel D, 100Ω differential impedance.
11 TD_M_D bidirectional Differential transmit and receive signal (pair M) for 1000Base-T channel D, 100Ω differential impedance.
12 RBIAS input Bias resistor connection point; connect 11kΩ ±1% resistor to ground.
13 VDDA1P8_1 power_in External 1.8V ±5% analog power in three-power mode; requires 1µF and 0.1µF decoupling capacitors when used.
14 SON output Differential SGMII or fiber data output (pair N); AC-coupled with 0.1µF capacitor; LVDS signal.
15 SOP output Differential SGMII or fiber data output (pair P); AC-coupled with 0.1µF capacitor; LVDS signal.
16 SIP input Differential SGMII or fiber data input (pair P); AC-coupled with 0.1µF capacitor; receives LVDS signal.
17 SIN input Differential SGMII or fiber data input (pair N); AC-coupled with 0.1µF capacitor; receives LVDS signal.
18 VDDIO power_in I/O power supply 1.8V, 2.5V, or 3.3V ±5%; requires 1µF and 0.1µF decoupling capacitors to ground.
19 XO output Crystal oscillator output for 25MHz crystal; keep floating if using external clock oscillator.
20 XI input Crystal oscillator input for 25MHz crystal or external oscillator; VIH ≥ 1.2V, VIL ≤ 0.6V.
21 JTAG_CLK/TX_ER input JTAG test clock (IEEE 1149.1 compliant) or MII transmit error signal from MAC; weak pull-up.
22 JTAG_TDO/GPIO_1 output JTAG test data output or configurable general-purpose I/O; see GPIO_MUX_CTRL register.
23 JTAG_TMS input JTAG test mode select for TAP controller (IEEE 1149.1); weak pull-up; TI recommends holding high with 3 clock cycles to reset.
24 JTAG_TDI/SD input JTAG test data input (IEEE 1149.1) or signal detect input for 1000Base-X/100Base-FX (low-active); weak pull-up.
25 TX_D3 input Transmit data bit 3 from MAC; synchronous with GTX_CLK (RGMII) or TX_CLK (MII); weak pull-down.
26 TX_D2 input Transmit data bit 2 from MAC; synchronous with GTX_CLK (RGMII) or TX_CLK (MII); weak pull-down.
27 TX_D1 input Transmit data bit 1 from MAC; synchronous with GTX_CLK (RGMII) or TX_CLK (MII); weak pull-down.
28 TX_D0 input Transmit data bit 0 from MAC; synchronous with GTX_CLK (RGMII) or TX_CLK (MII); weak pull-down.
29 GTX_CLK/TX_CLK bidirectional RGMII transmit clock (input at 125MHz for 1000Mbps) or MII transmit clock (output providing 25MHz for 100Mbps, 2.5MHz for 10Mbps); weak pull-down.
30 VDDIO power_in I/O power supply 1.8V, 2.5V, or 3.3V ±5%; requires 1µF and 0.1µF decoupling capacitors to ground.
31 VDD1P1 power_in 1.1V digital power supply ±10%; requires 1µF and 0.1µF decoupling capacitors to ground.
32 RX_CLK output Recovered receive clock for RGMII/MII modes; 125MHz (1000Mbps), 25MHz (100Mbps), or 2.5MHz (10Mbps); also strap configuration pin; weak pull-down.
33 RX_D0 output Receive data bit 0 to MAC; decoded from cable symbols; also strap configuration pin (4-level); weak pull-down.
34 RX_D1 output Receive data bit 1 to MAC; decoded from cable symbols; also strap configuration pin (4-level); weak pull-down.
35 RX_D2 output Receive data bit 2 to MAC; decoded from cable symbols; also strap configuration pin; weak pull-down.
36 RX_D3 output Receive data bit 3 to MAC; decoded from cable symbols; also strap configuration pin; weak pull-down.
37 TX_CTRL/TX_EN input RGMII transmit control (combines TX_EN and TX_ER via dual-edge encoding) or MII transmit enable from MAC; weak pull-down.
38 RX_CTRL/RX_DV output RGMII receive control (combines RX_DV and RX_ER via dual-edge encoding) or MII receive data valid to MAC; also mirror mode strap; weak pull-down.
39 VDD1P1 power_in 1.1V digital power supply ±10%; requires 1µF and 0.1µF decoupling capacitors to ground.
40 CLK_OUT output Configurable clock output (25MHz, 125MHz recovered clock, or TX clock); high impedance output.
41 MDIO bidirectional Serial management data I/O (open-drain); requires external 1.5kΩ pull-up resistor to VDDIO.
42 MDC input Serial management interface clock; maximum 25MHz; asynchronous to MAC transmit/receive clocks.
43 RESET_N input Active-low hardware reset input; minimum 1µs pulse duration required; in IO voltage domain; use 100Ω series resistor and 47µF capacitor to ground.
44 INT_N/PWDN_N bidirectional Interrupt output (open-drain, active-low) or power-down input (active-low); configurable via register; recommend 2.2kΩ external pull-up to VDDIO.
45 LED_2/GPIO_0 bidirectional LED2 output or configurable GPIO; part of VDDIO voltage domain; also strap configuration pin; weak pull-down.
46 LED_1/RX_ER output LED1 output or MII receive error signal to MAC; part of VDDIO voltage domain; also strap configuration pin; weak pull-down.
47 LED_0 output LED0 output in VDDIO voltage domain; also strap configuration pin (ANEG_DIS); weak pull-down.
48 VDDA1P8_2 power_in External 1.8V ±5% analog power in three-power mode; requires 1µF and 0.1µF decoupling capacitors when used.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Interface
Pins 49

CAD (KiCad official)

  • Symbol: DP83869HMRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: dp83869hmrgzr-etched.step / dp83869hmrgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83869hmrgzr.step / dp83869hmrgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (136 pp, sha256 c9f251ea9e61fb66, retrieved 2026-09-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF