# DP83630SQX

**Texas Instruments** · Ethernet Transceivers · QFN-48-EP(7x7)

DP83630SQX from Texas Instruments, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TX_CLK | output | MII transmit clock output (25 MHz at 100 Mb/s, 2.5 MHz at 10 Mb/s) derived from reference clock; outputs 50 MHz in RMII Master mode. |
| 2 | TX_EN | input | MII transmit enable input; active high indicates valid data on TXD[3:0] (MII) or TXD[1:0] (RMII). |
| 3 | TXD_0 | input | MII transmit data bit 0 input synchronous to TX_CLK. |
| 4 | TXD_1 | input | MII transmit data bit 1 input synchronous to TX_CLK. |
| 5 | TXD_2 | input | MII transmit data bit 2 input synchronous to TX_CLK. |
| 6 | TXD_3 | input | MII transmit data bit 3 input or RMII bit 1; also RMII_MAS strap pin for RMII Master mode configuration. |
| 7 | PWRDOWN/INTN | input | Power down input (asserted low enables low power mode) or programmable interrupt output (active low); register access required for configuration. |
| 8 | TCK | input | JTAG test clock input with internal pullup. |
| 9 | TDO | output | JTAG test data output; also usable as GPIO10 for IEEE 1588 event capture or triggering. |
| 10 | TMS | input | JTAG test mode select input with internal pullup. |
| 11 | TRST# | input | JTAG test reset input (active low) with internal pullup. |
| 12 | TDI | input | JTAG test data input with internal pullup; also usable as GPIO11 for IEEE 1588 event capture or triggering. |
| 13 | RD- | bidirectional | Differential receive input pair for 100BASE-TX or 10BASE-T signaling; Auto-MDIX capable for transmit in crossed mode. |
| 14 | RD+ | bidirectional | Differential receive input pair for 100BASE-TX or 10BASE-T signaling; Auto-MDIX capable for transmit in crossed mode. |
| 15 | CD_VSS | power_in | Analog ground for Common Mode Drive reference. |
| 16 | TD- | bidirectional | Differential transmit pair output for 10BASE-T or 100BASE-TX signaling; Auto-MDIX capable for receive in crossed mode. |
| 17 | TD+ | bidirectional | Differential transmit pair output for 10BASE-T or 100BASE-TX signaling; Auto-MDIX capable for receive in crossed mode. |
| 18 | ANAVSS | power_in | Analog ground. |
| 19 | ANA33VDD | power_in | Analog 3.3V supply voltage. |
| 20 | VREF | power_in | Bias resistor connection point; connect 4.87 kΩ ±1% resistor to GND for proper operation. |
| 21 | GPIO1 | bidirectional | General purpose I/O for IEEE 1588 event capture or triggering; also CLK_OUT_EN strap pin for clock output enable. |
| 22 | GPIO2 | bidirectional | General purpose I/O for IEEE 1588 event capture or triggering; also PCF_EN strap pin for PHY Control Frame enable. |
| 23 | GPIO3 | bidirectional | General purpose I/O for IEEE 1588 event capture or triggering. |
| 24 | CLK_OUT | bidirectional | Configurable clock output (default 25 MHz synchronized to PTP clock) or external IEEE 1588 reference clock input; also GPIO12. |
| 25 | GPIO4 | bidirectional | General purpose I/O for IEEE 1588 event capture or triggering. |
| 26 | LED_ACT | output | Activity LED output (on when transmit or receive active); also GPIO5 for IEEE 1588 functions (disable LED function via LEDCR register). |
| 27 | LED_SPEED/FX_SD | output | Speed LED output (on at 100 Mb/s, off at 10 Mb/s); also 100BASE-FX Signal Detect input; also GPIO6 for IEEE 1588 functions. |
| 28 | LED_LINK | output | Link LED output (on when link established); also GPIO7 for IEEE 1588 functions (disable LED function via LEDCR register). |
| 29 | RESET_N | input | Active low reset input with internal pullup; assert low for ≥1 µs to initialize device with all registers reset to default. |
| 30 | MDIO | bidirectional | Bi-directional serial management data I/O (requires 1.5 kΩ external pullup resistor or enable internal pullup via register). |
| 31 | MDC | input | Management data clock input for serial management interface; maximum clock rate 25 MHz. |
| 32 | IO_VDD | power_in | I/O supply voltage (3.3V nominal or 2.5V operating range). |
| 33 | X2 | output | Crystal oscillator output; connect to external 25 MHz crystal or leave unconnected when using external CMOS oscillator. |
| 34 | X1 | input | Crystal oscillator input; connect to 25 MHz ±50 ppm crystal (with X2) or external CMOS oscillator source; 50 MHz for RMII Slave mode. |
| 35 | IO_CORE_VSS | power_in | Digital ground. |
| 36 | GPIO8 | bidirectional | General purpose I/O with internal pulldown for IEEE 1588 event capture or triggering. |
| 37 | GPIO9 | bidirectional | General purpose I/O for IEEE 1588 event capture or triggering. |
| 38 | RX_CLK | output | MII receive clock output (25 MHz at 100 Mb/s, 2.5 MHz at 10 Mb/s); outputs 50 MHz in RMII Master mode. |
| 39 | RX_DV | output | MII/RMII receive data valid output (asserted high when valid data present); also MII_MODE strap pin for interface mode selection. |
| 40 | CRS/CRS_DV | output | MII carrier sense or RMII CRS/RX_DV combined output; also LED_CFG strap pin for LED mode configuration. |
| 41 | RX_ER | output | MII receive error output (asserted high for invalid symbols in 100 Mb/s mode); also FX_EN_Z strap pin to enable 100BASE-FX fiber mode. |
| 42 | COL | output | MII collision detection output (asserted high in half-duplex for collision or ~1 µs heartbeat pulse at end of 10BASE-T packet); also PHYAD0 strap bit. |
| 43 | RXD_3 | output | MII receive data bit 3 or RMII bit 1 output synchronous to RX_CLK/X1; also PHYAD1 strap bit for PHY address. |
| 44 | RXD_2 | output | MII receive data bit 2 or RMII bit 0 output synchronous to RX_CLK/X1; also PHYAD2 strap bit for PHY address. |
| 45 | RXD_1 | output | MII receive data bit 1 output synchronous to RX_CLK/X1; also PHYAD3 strap bit for PHY address. |
| 46 | RXD_0 | output | MII receive data bit 0 output synchronous to RX_CLK/X1; also PHYAD4 strap bit for PHY address. |
| 47 | IO_VSS | power_in | Digital ground. |
| 48 | IO_VDD | power_in | I/O supply voltage (3.3V nominal or 2.5V operating range). |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-48-EP(7x7) |
| Category | Interface |
| Pins | 49 |

## CAD (KiCad official)

- Symbol: `DP83630SQX`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `dp83630sqx-etched.step` / `dp83630sqx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83630sqx.step` / `dp83630sqx.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dp83630) (138 pp, sha256 `a9aca94ad57ffe39`, retrieved 2026-10-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dp83630sqx-datasheet.pdf)