component
DP83630SQX
Public Made by Adomby adom
Texas Instruments Ethernet Transceivers, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+85@@ -0,0 +1,85 @@+# DP83630SQX++**Texas Instruments** · Ethernet Transceivers · QFN-48-EP(7x7)++DP83630SQX from Texas Instruments, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | TX_CLK | output | MII transmit clock output (25 MHz at 100 Mb/s, 2.5 MHz at 10 Mb/s) derived from reference clock; outputs 50 MHz in RMII Master mode. |+| 2 | TX_EN | input | MII transmit enable input; active high indicates valid data on TXD[3:0] (MII) or TXD[1:0] (RMII). |+| 3 | TXD_0 | input | MII transmit data bit 0 input synchronous to TX_CLK. |+| 4 | TXD_1 | input | MII transmit data bit 1 input synchronous to TX_CLK. |+| 5 | TXD_2 | input | MII transmit data bit 2 input synchronous to TX_CLK. |+| 6 | TXD_3 | input | MII transmit data bit 3 input or RMII bit 1; also RMII_MAS strap pin for RMII Master mode configuration. |+| 7 | PWRDOWN/INTN | input | Power down input (asserted low enables low power mode) or programmable interrupt output (active low); register access required for configuration. |+| 8 | TCK | input | JTAG test clock input with internal pullup. |+| 9 | TDO | output | JTAG test data output; also usable as GPIO10 for IEEE 1588 event capture or triggering. |+| 10 | TMS | input | JTAG test mode select input with internal pullup. |+| 11 | TRST# | input | JTAG test reset input (active low) with internal pullup. |+| 12 | TDI | input | JTAG test data input with internal pullup; also usable as GPIO11 for IEEE 1588 event capture or triggering. |+| 13 | RD- | bidirectional | Differential receive input pair for 100BASE-TX or 10BASE-T signaling; Auto-MDIX capable for transmit in crossed mode. |+| 14 | RD+ | bidirectional | Differential receive input pair for 100BASE-TX or 10BASE-T signaling; Auto-MDIX capable for transmit in crossed mode. |+| 15 | CD_VSS | power_in | Analog ground for Common Mode Drive reference. |+| 16 | TD- | bidirectional | Differential transmit pair output for 10BASE-T or 100BASE-TX signaling; Auto-MDIX capable for receive in crossed mode. |+| 17 | TD+ | bidirectional | Differential transmit pair output for 10BASE-T or 100BASE-TX signaling; Auto-MDIX capable for receive in crossed mode. |+| 18 | ANAVSS | power_in | Analog ground. |+| 19 | ANA33VDD | power_in | Analog 3.3V supply voltage. |+| 20 | VREF | power_in | Bias resistor connection point; connect 4.87 kΩ ±1% resistor to GND for proper operation. |+| 21 | GPIO1 | bidirectional | General purpose I/O for IEEE 1588 event capture or triggering; also CLK_OUT_EN strap pin for clock output enable. |+| 22 | GPIO2 | bidirectional | General purpose I/O for IEEE 1588 event capture or triggering; also PCF_EN strap pin for PHY Control Frame enable. |+| 23 | GPIO3 | bidirectional | General purpose I/O for IEEE 1588 event capture or triggering. |+| 24 | CLK_OUT | bidirectional | Configurable clock output (default 25 MHz synchronized to PTP clock) or external IEEE 1588 reference clock input; also GPIO12. |+| 25 | GPIO4 | bidirectional | General purpose I/O for IEEE 1588 event capture or triggering. |+| 26 | LED_ACT | output | Activity LED output (on when transmit or receive active); also GPIO5 for IEEE 1588 functions (disable LED function via LEDCR register). |+| 27 | LED_SPEED/FX_SD | output | Speed LED output (on at 100 Mb/s, off at 10 Mb/s); also 100BASE-FX Signal Detect input; also GPIO6 for IEEE 1588 functions. |+| 28 | LED_LINK | output | Link LED output (on when link established); also GPIO7 for IEEE 1588 functions (disable LED function via LEDCR register). |+| 29 | RESET_N | input | Active low reset input with internal pullup; assert low for ≥1 µs to initialize device with all registers reset to default. |+| 30 | MDIO | bidirectional | Bi-directional serial management data I/O (requires 1.5 kΩ external pullup resistor or enable internal pullup via register). |+| 31 | MDC | input | Management data clock input for serial management interface; maximum clock rate 25 MHz. |+| 32 | IO_VDD | power_in | I/O supply voltage (3.3V nominal or 2.5V operating range). |+| 33 | X2 | output | Crystal oscillator output; connect to external 25 MHz crystal or leave unconnected when using external CMOS oscillator. |+| 34 | X1 | input | Crystal oscillator input; connect to 25 MHz ±50 ppm crystal (with X2) or external CMOS oscillator source; 50 MHz for RMII Slave mode. |+| 35 | IO_CORE_VSS | power_in | Digital ground. |+| 36 | GPIO8 | bidirectional | General purpose I/O with internal pulldown for IEEE 1588 event capture or triggering. |+| 37 | GPIO9 | bidirectional | General purpose I/O for IEEE 1588 event capture or triggering. |+| 38 | RX_CLK | output | MII receive clock output (25 MHz at 100 Mb/s, 2.5 MHz at 10 Mb/s); outputs 50 MHz in RMII Master mode. |+| 39 | RX_DV | output | MII/RMII receive data valid output (asserted high when valid data present); also MII_MODE strap pin for interface mode selection. |+| 40 | CRS/CRS_DV | output | MII carrier sense or RMII CRS/RX_DV combined output; also LED_CFG strap pin for LED mode configuration. |+| 41 | RX_ER | output | MII receive error output (asserted high for invalid symbols in 100 Mb/s mode); also FX_EN_Z strap pin to enable 100BASE-FX fiber mode. |+| 42 | COL | output | MII collision detection output (asserted high in half-duplex for collision or ~1 µs heartbeat pulse at end of 10BASE-T packet); also PHYAD0 strap bit. |+| 43 | RXD_3 | output | MII receive data bit 3 or RMII bit 1 output synchronous to RX_CLK/X1; also PHYAD1 strap bit for PHY address. |+| 44 | RXD_2 | output | MII receive data bit 2 or RMII bit 0 output synchronous to RX_CLK/X1; also PHYAD2 strap bit for PHY address. |+| 45 | RXD_1 | output | MII receive data bit 1 output synchronous to RX_CLK/X1; also PHYAD3 strap bit for PHY address. |+| 46 | RXD_0 | output | MII receive data bit 0 output synchronous to RX_CLK/X1; also PHYAD4 strap bit for PHY address. |+| 47 | IO_VSS | power_in | Digital ground. |+| 48 | IO_VDD | power_in | I/O supply voltage (3.3V nominal or 2.5V operating range). |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | QFN-48-EP(7x7) |+| Category | Interface |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `DP83630SQX`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `dp83630sqx-etched.step` / `dp83630sqx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83630sqx.step` / `dp83630sqx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dp83630) (138 pp, sha256 `a9aca94ad57ffe39`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dp83630sqx-datasheet.pdf)
page.jsonadded+445@@ -0,0 +1,445 @@+{+ "slug": "dp83630sqx",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Ethernet Transceivers, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "dp83630sqx",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dp83630sqx.kicad_sym",+ "dp83630sqx.kicad_mod",+ "dp83630sqx.glb",+ "dp83630sqx.step",+ "dp83630sqx.lbr",+ "docs/hero.png",+ "docs/dp83630sqx-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "dp83630sqx-hero.glb",+ "dp83630sqx-hero.overlay.json"+ ],+ "component": {+ "mpn": "DP83630SQX",+ "manufacturer": "Texas Instruments",+ "package": "QFN-48-EP(7x7)",+ "pin_count": 49,+ "category": "Interface",+ "subcategory": "Ethernet Transceivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dp83630",+ "parts": {+ "symbol": "dp83630sqx.kicad_sym",+ "footprint": "dp83630sqx.kicad_mod",+ "model_3d": "dp83630sqx-hero.glb",+ "model_3d_plain": "dp83630sqx.glb",+ "model_3d_step": "dp83630sqx-etched.step",+ "model_3d_step_plain": "dp83630sqx.step",+ "lbr": "dp83630sqx.lbr"+ },+ "distributor_links": {+ "lcsc": "C2671567"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T02:09:02Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "TX_CLK",+ "type": "output",+ "description": "MII transmit clock output (25 MHz at 100 Mb/s, 2.5 MHz at 10 Mb/s) derived from reference clock; outputs 50 MHz in RMII Master mode."+ },+ {+ "number": "2",+ "name": "TX_EN",+ "type": "input",+ "description": "MII transmit enable input; active high indicates valid data on TXD[3:0] (MII) or TXD[1:0] (RMII)."+ },+ {+ "number": "3",+ "name": "TXD_0",+ "type": "input",+ "description": "MII transmit data bit 0 input synchronous to TX_CLK."+ },+ {+ "number": "4",+ "name": "TXD_1",+ "type": "input",+ "description": "MII transmit data bit 1 input synchronous to TX_CLK."+ },+ {+ "number": "5",+ "name": "TXD_2",+ "type": "input",+ "description": "MII transmit data bit 2 input synchronous to TX_CLK."+ },+ {+ "number": "6",+ "name": "TXD_3",+ "type": "input",+ "description": "MII transmit data bit 3 input or RMII bit 1; also RMII_MAS strap pin for RMII Master mode configuration."+ },+ {+ "number": "7",+ "name": "PWRDOWN/INTN",+ "type": "input",+ "description": "Power down input (asserted low enables low power mode) or programmable interrupt output (active low); register access required for configuration."+ },+ {+ "number": "8",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock input with internal pullup."+ },+ {+ "number": "9",+ "name": "TDO",+ "type": "output",+ "description": "JTAG test data output; also usable as GPIO10 for IEEE 1588 event capture or triggering."+ },+ {+ "number": "10",+ "name": "TMS",+ "type": "input",+ "description": "JTAG test mode select input with internal pullup."+ },+ {+ "number": "11",+ "name": "TRST#",+ "type": "input",+ "description": "JTAG test reset input (active low) with internal pullup."+ },+ {+ "number": "12",+ "name": "TDI",+ "type": "input",+ "description": "JTAG test data input with internal pullup; also usable as GPIO11 for IEEE 1588 event capture or triggering."+ },+ {+ "number": "13",+ "name": "RD-",+ "type": "bidirectional",+ "description": "Differential receive input pair for 100BASE-TX or 10BASE-T signaling; Auto-MDIX capable for transmit in crossed mode."+ },+ {+ "number": "14",+ "name": "RD+",+ "type": "bidirectional",+ "description": "Differential receive input pair for 100BASE-TX or 10BASE-T signaling; Auto-MDIX capable for transmit in crossed mode."+ },+ {+ "number": "15",+ "name": "CD_VSS",+ "type": "power_in",+ "description": "Analog ground for Common Mode Drive reference."+ },+ {+ "number": "16",+ "name": "TD-",+ "type": "bidirectional",+ "description": "Differential transmit pair output for 10BASE-T or 100BASE-TX signaling; Auto-MDIX capable for receive in crossed mode."+ },+ {+ "number": "17",+ "name": "TD+",+ "type": "bidirectional",+ "description": "Differential transmit pair output for 10BASE-T or 100BASE-TX signaling; Auto-MDIX capable for receive in crossed mode."+ },+ {+ "number": "18",+ "name": "ANAVSS",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "19",+ "name": "ANA33VDD",+ "type": "power_in",+ "description": "Analog 3.3V supply voltage."+ },+ {+ "number": "20",+ "name": "VREF",+ "type": "power_in",+ "description": "Bias resistor connection point; connect 4.87 kΩ ±1% resistor to GND for proper operation."+ },+ {+ "number": "21",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General purpose I/O for IEEE 1588 event capture or triggering; also CLK_OUT_EN strap pin for clock output enable."+ },+ {+ "number": "22",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General purpose I/O for IEEE 1588 event capture or triggering; also PCF_EN strap pin for PHY Control Frame enable."+ },+ {+ "number": "23",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General purpose I/O for IEEE 1588 event capture or triggering."+ },+ {+ "number": "24",+ "name": "CLK_OUT",+ "type": "bidirectional",+ "description": "Configurable clock output (default 25 MHz synchronized to PTP clock) or external IEEE 1588 reference clock input; also GPIO12."+ },+ {+ "number": "25",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General purpose I/O for IEEE 1588 event capture or triggering."+ },+ {+ "number": "26",+ "name": "LED_ACT",+ "type": "output",+ "description": "Activity LED output (on when transmit or receive active); also GPIO5 for IEEE 1588 functions (disable LED function via LEDCR register)."+ },+ {+ "number": "27",+ "name": "LED_SPEED/FX_SD",+ "type": "output",+ "description": "Speed LED output (on at 100 Mb/s, off at 10 Mb/s); also 100BASE-FX Signal Detect input; also GPIO6 for IEEE 1588 functions."+ },+ {+ "number": "28",+ "name": "LED_LINK",+ "type": "output",+ "description": "Link LED output (on when link established); also GPIO7 for IEEE 1588 functions (disable LED function via LEDCR register)."+ },+ {+ "number": "29",+ "name": "RESET_N",+ "type": "input",+ "description": "Active low reset input with internal pullup; assert low for ≥1 µs to initialize device with all registers reset to default."+ },+ {+ "number": "30",+ "name": "MDIO",+ "type": "bidirectional",+ "description": "Bi-directional serial management data I/O (requires 1.5 kΩ external pullup resistor or enable internal pullup via register)."+ },+ {+ "number": "31",+ "name": "MDC",+ "type": "input",+ "description": "Management data clock input for serial management interface; maximum clock rate 25 MHz."+ },+ {+ "number": "32",+ "name": "IO_VDD",+ "type": "power_in",+ "description": "I/O supply voltage (3.3V nominal or 2.5V operating range)."+ },+ {+ "number": "33",+ "name": "X2",+ "type": "output",+ "description": "Crystal oscillator output; connect to external 25 MHz crystal or leave unconnected when using external CMOS oscillator."+ },+ {+ "number": "34",+ "name": "X1",+ "type": "input",+ "description": "Crystal oscillator input; connect to 25 MHz ±50 ppm crystal (with X2) or external CMOS oscillator source; 50 MHz for RMII Slave mode."+ },+ {+ "number": "35",+ "name": "IO_CORE_VSS",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "36",+ "name": "GPIO8",+ "type": "bidirectional",+ "description": "General purpose I/O with internal pulldown for IEEE 1588 event capture or triggering."+ },+ {+ "number": "37",+ "name": "GPIO9",+ "type": "bidirectional",+ "description": "General purpose I/O for IEEE 1588 event capture or triggering."+ },+ {+ "number": "38",+ "name": "RX_CLK",+ "type": "output",+ "description": "MII receive clock output (25 MHz at 100 Mb/s, 2.5 MHz at 10 Mb/s); outputs 50 MHz in RMII Master mode."+ },+ {+ "number": "39",+ "name": "RX_DV",+ "type": "output",+ "description": "MII/RMII receive data valid output (asserted high when valid data present); also MII_MODE strap pin for interface mode selection."+ },+ {+ "number": "40",+ "name": "CRS/CRS_DV",+ "type": "output",+ "description": "MII carrier sense or RMII CRS/RX_DV combined output; also LED_CFG strap pin for LED mode configuration."+ },+ {+ "number": "41",+ "name": "RX_ER",+ "type": "output",+ "description": "MII receive error output (asserted high for invalid symbols in 100 Mb/s mode); also FX_EN_Z strap pin to enable 100BASE-FX fiber mode."+ },+ {+ "number": "42",+ "name": "COL",+ "type": "output",+ "description": "MII collision detection output (asserted high in half-duplex for collision or ~1 µs heartbeat pulse at end of 10BASE-T packet); also PHYAD0 strap bit."+ },+ {+ "number": "43",+ "name": "RXD_3",+ "type": "output",+ "description": "MII receive data bit 3 or RMII bit 1 output synchronous to RX_CLK/X1; also PHYAD1 strap bit for PHY address."+ },+ {+ "number": "44",+ "name": "RXD_2",+ "type": "output",+ "description": "MII receive data bit 2 or RMII bit 0 output synchronous to RX_CLK/X1; also PHYAD2 strap bit for PHY address."+ },+ {+ "number": "45",+ "name": "RXD_1",+ "type": "output",+ "description": "MII receive data bit 1 output synchronous to RX_CLK/X1; also PHYAD3 strap bit for PHY address."+ },+ {+ "number": "46",+ "name": "RXD_0",+ "type": "output",+ "description": "MII receive data bit 0 output synchronous to RX_CLK/X1; also PHYAD4 strap bit for PHY address."+ },+ {+ "number": "47",+ "name": "IO_VSS",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "48",+ "name": "IO_VDD",+ "type": "power_in",+ "description": "I/O supply voltage (3.3V nominal or 2.5V operating range)."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: PWRDOWN/INTN pin function depends on register configuration: default is power down input, but can be; Multiple pins serve dual or triple functions (strap options + primary function + GPIO capability); v; DAP (Die Attach Pad) is optional: connection to GND plane is recommended for thermal performance, bu",+ "exposed pad 49 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 32,+ "cost_usd": 0.3391,+ "at": "2026-10-07T02:08:33"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dp83630",+ "pages": 138,+ "sha256": "a9aca94ad57ffe39",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dp83630sqx.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dp83630sqx-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "ce07fd56b0628d012466f4448ac18ae81a0a5b451d2f68e1aa6fa5059ca4da93",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}