component
DMT10H009LSS-13
Public Made by Adomby adom
Diodes Incorporated MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownDMT10H009LSS-13
Diodes Incorporated · MOSFETs · SO-8
DMT10H009LSS-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol and footprint from KiCad-official CAD; the 3D model is generated from the datasheet's package dimensions.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the 100V N-channel MOSFET, tied internally with pins 2 and 3. |
| 2 | S | passive | Source terminal of the 100V N-channel MOSFET, tied internally with pins 1 and 3. |
| 3 | S | passive | Source terminal of the 100V N-channel MOSFET, tied internally with pins 1 and 2. |
| 4 | G | input | Gate terminal, rated VGSS ±20V, with VGS(TH) of 1.3V to 2.5V at ID = 250µA. |
| 5 | D | passive | Drain terminal, VDSS 100V, tied internally with pins 6, 7 and 8. |
| 6 | D | passive | Drain terminal, VDSS 100V, tied internally with pins 5, 7 and 8. |
| 7 | D | passive | Drain terminal, VDSS 100V, tied internally with pins 5, 6 and 8. |
| 8 | D | passive | Drain terminal, VDSS 100V, tied internally with pins 5, 6 and 7. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Triode/MOS Tube/Transistor |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | 100 | V | VGS = 0V, ID = 1mA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 1 | μA | VDS = 80V, VGS = 0V | 2 | ||
| Gate-Source Leakage | IGSS | -100 | 100 | nA | VGS = ±20V, VDS = 0V | 2 | |
| Gate Threshold Voltage | VGS(TH) | 1.3 | 2.5 | V | VDS = VGS, ID = 250μA | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 7.1 | 9 | mΩ | VGS = 10V, ID = 10A | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 9.7 | 13.8 | mΩ | VGS = 4.5V, ID = 6A | 2 | |
| Diode Forward Voltage | VSD | 0.8 | 1.2 | V | VGS = 0V, IS = 20A | 2 | |
| Drain-Source Voltage | VDSS | 100 | V | TA = +25°C | 2 | ||
| Gate-Source Voltage | VGSS | -20 | 20 | V | TA = +25°C | 2 | |
| Continuous Drain Current | ID | 13 | A | VGS = 10V, TA = +25°C (Note 6) | 2 | ||
| Continuous Drain Current | ID | 10 | A | VGS = 10V, TA = +70°C (Note 6) | 2 | ||
| Continuous Drain Current | ID | 48 | A | VGS = 10V, TC = +25°C | 2 | ||
| Continuous Drain Current | ID | 38 | A | VGS = 10V, TC = +70°C | 2 | ||
| Pulsed Drain Current | IDM | 110 | A | 10µs Pulse, Duty Cycle = 1% | 2 | ||
| Maximum Continuous Body Diode Forward Current | IS | 2.5 | A | Note 6 | 2 | ||
| Pulsed Body Diode Forward Current | ISM | 110 | A | 10µs Pulse, Duty Cycle = 1% | 2 | ||
| Avalanche Current | IAS | 21 | A | L = 0.3mH | 2 | ||
| Avalanche Energy | EAS | 66 | mJ | L = 0.3mH | 2 | ||
| Total Power Dissipation | PD | 1.8 | W | Note 5, TA = +25°C | 2 | ||
| Total Power Dissipation | PD | 2.5 | W | Note 6, TA = +25°C | 2 | ||
| Thermal Resistance, Junction to Ambient | RϴJA | 68 | °C/W | Note 5 | 2 | ||
| Thermal Resistance, Junction to Ambient | RϴJA | 50 | °C/W | Note 6 | 2 | ||
| Thermal Resistance, Junction to Case | RϴJC | 4 | °C/W | Note 6 | 2 | ||
| Operating and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 2 | ||
| Input Capacitance | Ciss | 2309 | pF | VDS = 50V, VGS = 0V, f = 1MHz | 2 | ||
| Output Capacitance | Coss | 536 | pF | VDS = 50V, VGS = 0V, f = 1MHz | 2 | ||
| Reverse Transfer Capacitance | Crss | 13.7 | pF | VDS = 50V, VGS = 0V, f = 1MHz | 2 | ||
| Gate Resistance | Rg | 1.9 | Ω | VDS = 0V, VGS = 0V, f = 1MHz | 2 | ||
| Total Gate Charge (VGS = 10V) | Qg | 40.2 | nC | VDD = 50V, ID = 20A | 2 | ||
| Total Gate Charge (VGS = 4.5V) | Qg | 20.2 | nC | VDD = 50V, ID = 20A | 2 | ||
| Gate-Source Charge | Qgs | 7 | nC | VDD = 50V, ID = 20A | 2 | ||
| Gate-Drain Charge | Qgd | 8.5 | nC | VDD = 50V, ID = 20A | 2 | ||
| Turn-On Delay Time | tD(ON) | 5.4 | ns | VDD = 50V, VGS = 10V, ID = 20A, Rg = 3Ω | 2 | ||
| Turn-On Rise Time | tR | 10.6 | ns | VDD = 50V, VGS = 10V, ID = 20A, Rg = 3Ω | 2 | ||
| Turn-Off Delay Time | tD(OFF) | 28.3 | ns | VDD = 50V, VGS = 10V, ID = 20A, Rg = 3Ω | 2 | ||
| Turn-Off Fall Time | tF | 14.9 | ns | VDD = 50V, VGS = 10V, ID = 20A, Rg = 3Ω | 2 | ||
| Body Diode Reverse Recovery Time | tRR | 44.3 | ns | IF = 20A, di/dt = 100A/μs | 2 | ||
| Body Diode Reverse Recovery Charge | QRR | 65.5 | nC | IF = 20A, di/dt = 100A/μs | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | Terminal Finish, Matte Tin Annealed over Copper Leadframe. | 1 |
CAD (land: KiCad; 3D: generated from the datasheet)
- Symbol:
DMT10H009LSS-13 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8, generated on the KiCad land (body 3.85 x 4.9 mm, terminals on the pads, 1.45 mm tall, datasheet A, nominal). KiCad's stock model for this land is taller than the datasheet allows, so the model is generated from the datasheet drawing; the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
- 3D model files:
dmt10h009lss-13-etched.step/dmt10h009lss-13-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmt10h009lss-13.step/dmt10h009lss-13.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (7 pp, sha256
de6ef5004fb1da8d, retrieved 2026-11-13, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: land: KiCad official libraries (CC-BY-SA 4.0); 3D: generated from the datasheet's package dimensions (provenance.model_3d_generated).