component
DMN61D8LVTQ-7
Public Made by Adomby adom
Diodes Incorporated MOSFETs, TSOT-26. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DMN61D8LVTQ-7
Diodes Incorporated · MOSFETs · TSOT-26
DMN61D8LVTQ-7 from Diodes Incorporated, in a TSOT-26. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of channel 1 MOSFET, connected to the 100 ohm gate-protection network and the ESD-protected gate structure in the equivalent circuit. |
| 2 | G1 | input | ESD-protected logic-level gate input of channel 1 with an internal 10 kohm series resistor and 100 kohm gate-to-source resistor, rated VGSS ±12 V. |
| 3 | D2 | passive | Drain of channel 2 MOSFET with internal active clamp for inductive loads, rated VDSS 60 V and ID 630 mA at TA = +25°C. |
| 4 | S2 | passive | Source of channel 2 MOSFET, returned to ground as the low-side switch reference. |
| 5 | G2 | input | ESD-protected logic-level gate input of channel 2 with an internal 10 kohm series resistor and 100 kohm gate-to-source resistor, rated VGSS ±12 V. |
| 6 | D1 | passive | Drain of channel 1 MOSFET with internal active clamp for inductive loads, rated VDSS 60 V and ID 630 mA at TA = +25°C. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | TSOT-26 |
| Category | Transistors/Thyristors |
| Pins | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | • Terminals Connections: See Diagram • Terminals: Finish, Matte Tin Annealed over Copper Leadframe; | 1 |
CAD (KiCad official)
- Symbol:
DMN61D8LVTQ-7 - Footprint:
Package_TO_SOT_SMD:TSOT-23-6 - 3D model: TSOT-26 (KiCad packages3D, STEP)
- 3D model files:
dmn61d8lvtq-7-etched.step/dmn61d8lvtq-7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmn61d8lvtq-7.step/dmn61d8lvtq-7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (7 pp, sha256
d00a8496d1ba3adc, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DMN61D8LVTQ-7
**Diodes Incorporated** · MOSFETs · TSOT-26
DMN61D8LVTQ-7 from Diodes Incorporated, in a TSOT-26. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of channel 1 MOSFET, connected to the 100 ohm gate-protection network and the ESD-protected gate structure in the equivalent circuit. |
| 2 | G1 | input | ESD-protected logic-level gate input of channel 1 with an internal 10 kohm series resistor and 100 kohm gate-to-source resistor, rated VGSS ±12 V. |
| 3 | D2 | passive | Drain of channel 2 MOSFET with internal active clamp for inductive loads, rated VDSS 60 V and ID 630 mA at TA = +25°C. |
| 4 | S2 | passive | Source of channel 2 MOSFET, returned to ground as the low-side switch reference. |
| 5 | G2 | input | ESD-protected logic-level gate input of channel 2 with an internal 10 kohm series resistor and 100 kohm gate-to-source resistor, rated VGSS ±12 V. |
| 6 | D1 | passive | Drain of channel 1 MOSFET with internal active clamp for inductive loads, rated VDSS 60 V and ID 630 mA at TA = +25°C. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | TSOT-26 |
| Category | Transistors/Thyristors |
| Pins | 6 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | • Terminals Connections: See Diagram • Terminals: Finish, Matte Tin Annealed over Copper Leadframe; | 1 |
## CAD (KiCad official)
- Symbol: `DMN61D8LVTQ-7`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-6`
- 3D model: TSOT-26 (KiCad packages3D, STEP)
- 3D model files: `dmn61d8lvtq-7-etched.step` / `dmn61d8lvtq-7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmn61d8lvtq-7.step` / `dmn61d8lvtq-7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Diodes Incorporated datasheet](https://www.diodes.com/assets/Datasheets/DMN61D8LVTQ-7.pdf) (7 pp, sha256 `d00a8496d1ba3adc`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dmn61d8lvtq-7-datasheet.pdf)