# DMN601DMK-7

**Diodes Incorporated** · MOSFETs · SOT-26

DMN601DMK-7 from Diodes Incorporated, in a SOT-26. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of MOSFET 1 (N-channel, 60V VDSS), per the top-view internal schematic. |
| 2 | G1 | input | Gate of MOSFET 1, with internal gate protection diode (ESD protected to 2kV), VGSS ±20V maximum. |
| 3 | D2 | passive | Drain of MOSFET 2 (60V VDSS, 510mA continuous ID at VGS=10V, TA=25°C). |
| 4 | S2 | passive | Source of MOSFET 2 (N-channel, 60V VDSS), per the top-view internal schematic. |
| 5 | G2 | input | Gate of MOSFET 2, with internal gate protection diode (ESD protected to 2kV), VGSS ±20V maximum. |
| 6 | D1 | passive | Drain of MOSFET 1 (60V VDSS, 510mA continuous ID at VGS=10V, TA=25°C). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-26 |
| Category | Transistors/Thyristors |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | 60 |  |  | V | VGS = 0V, ID = 10µA | 3 |
| Zero Gate Voltage Drain Current | IDSS |  |  | 1 | µA | VDS = 60V, VGS = 0V | 3 |
| Gate-Source Leakage | IGSS |  |  | 10 | µA | VGS = 20V, VDS = 0V | 3 |
| Gate Threshold Voltage | VGS(th) | 1 | 1.6 | 2.5 | V | VDS = 10V, ID = 1mA | 3 |
| Static Drain-Source On-Resistance | RDS(ON) |  |  | 2.4 | Ω | VGS = 10V, ID = 200mA | 3 |
| Static Drain-Source On-Resistance | RDS(ON) |  |  | 4 | Ω | VGS = 4V, ID = 200mA | 3 |
| Forward Transfer Admittance | /Yfs/ | 100 |  |  | mS | VDS = 10V, ID = 200mA | 3 |
| Diode Forward Voltage | VSD |  | 0.5 | 1.4 | V | VGS = 0V, IS = 115mA | 3 |
| Input Capacitance | Ciss |  | 30 | 50 | pF | VDS = 25V, VGS = 0V, f = 1.0MHz | 3 |
| Output Capacitance | Coss |  | 5 | 25 | pF | VDS = 25V, VGS = 0V, f = 1.0MHz | 3 |
| Reverse Transfer Capacitance | Crss |  | 3 | 5 | pF | VDS = 25V, VGS = 0V, f = 1.0MHz | 3 |
| Drain-Source Voltage | VDSS |  |  | 60 | V |  | 2 |
| Gate-Source Voltage | VGSS | -20 |  | 20 | V |  | 2 |
| Continuous Drain Current, steady state TA = +25°C | ID |  |  | 510 | mA | VGS = 10V, steady state (Note 6) | 2 |
| Continuous Drain Current, steady state TA = +70°C | ID |  |  | 400 | mA | VGS = 10V, steady state (Note 6) | 2 |
| Continuous Drain Current, t<10s TA = +25°C | ID |  |  | 580 | mA | VGS = 10V, t<10s (Note 6) | 2 |
| Continuous Drain Current, t<10s TA = +70°C | ID |  |  | 470 | mA | VGS = 10V, t<10s (Note 6) | 2 |
| Continuous Drain Current, steady state TA = +25°C | ID |  |  | 390 | mA | VGS = 4V, steady state (Note 6) | 2 |
| Continuous Drain Current, steady state TA = +70°C | ID |  |  | 300 | mA | VGS = 4V, steady state (Note 6) | 2 |
| Continuous Drain Current, t<10s TA = +25°C | ID |  |  | 440 | mA | VGS = 4V, t<10s (Note 6) | 2 |
| Continuous Drain Current, t<10s TA = +70°C | ID |  |  | 340 | mA | VGS = 4V, t<10s (Note 6) | 2 |
| Pulsed Drain Current | IDM |  |  | 850 | mA | 10µs Pulse, Duty Cycle = 1% | 2 |
| Maximum Body Diode Continuous Current | IS |  |  | 1.2 | A |  | 2 |
| Total Power Dissipation | PD |  |  | 0.7 | W | Note 5: FR-4 PC board, minimum recommended pad layout, single sided | 2 |
| Total Power Dissipation | PD |  |  | 0.98 | W | Note 6: FR-4, 2oz copper, thermal bias to bottom layer 1 inch square copper plate | 2 |
| Thermal Resistance, Junction to Ambient, steady state | RθJA |  |  | 157 | °C/W | Note 5 | 2 |
| Thermal Resistance, Junction to Ambient, t<10s | RθJA |  |  | 121 | °C/W | Note 5 | 2 |
| Thermal Resistance, Junction to Ambient, steady state | RθJA |  |  | 113 | °C/W | Note 6 | 2 |
| Thermal Resistance, Junction to Ambient, t<10s | RθJA |  |  | 88 | °C/W | Note 6 | 2 |
| Thermal Resistance, Junction to Case | RθJC |  |  | 26 | °C/W | Note 6 | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 |  | 150 | °C |  | 2 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin |  Terminal Connections: See Diagram  Terminals: Finish  Matte Tin Annealed over Copper | 1 |

## CAD (KiCad official)

- Symbol: `DMN601DMK-7`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-26 (KiCad packages3D, STEP)
- 3D model files: `dmn601dmk-7-etched.step` / `dmn601dmk-7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmn601dmk-7.step` / `dmn601dmk-7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Diodes Incorporated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586203485591785472) (7 pp, sha256 `a6d6ad47c58045dd`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dmn601dmk-7-datasheet.pdf)