component
DMN4800LSS-13
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Diodes Incorporated MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DMN4800LSS-13
Diodes Incorporated · MOSFETs · SO-8
DMN4800LSS-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the N-channel MOSFET, tied to the other source pins. |
| 2 | S | passive | Source terminal of the N-channel MOSFET, tied to the other source pins. |
| 3 | S | passive | Source terminal of the N-channel MOSFET, tied to the other source pins. |
| 4 | G | input | Gate terminal; gate-source voltage is rated at 25V maximum with a threshold of 0.8V to 1.6V. |
| 5 | D | passive | Drain terminal, rated at 30V VDSS and 8.6A continuous at TA=+25°C, tied to the other drain pins. |
| 6 | D | passive | Drain terminal, rated at 30V VDSS and 8.6A continuous at TA=+25°C, tied to the other drain pins. |
| 7 | D | passive | Drain terminal, rated at 30V VDSS and 8.6A continuous at TA=+25°C, tied to the other drain pins. |
| 8 | D | passive | Drain terminal, rated at 30V VDSS and 8.6A continuous at TA=+25°C, tied to the other drain pins. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS | 30 | V | 2 | |||
| Gate-Source Voltage | VGSS | 25 | V | 2 | |||
| Continuous Drain Current, steady state | ID | 8.6 | A | VGS = 10V, TA = +25°C, steady state | 2 | ||
| Continuous Drain Current, steady state | ID | 6.3 | A | VGS = 10V, TA = +70°C, steady state | 2 | ||
| Continuous Drain Current, t<10s | ID | 11.8 | A | VGS = 10V, TA = +25°C, t<10s | 2 | ||
| Continuous Drain Current, t<10s | ID | 9 | A | VGS = 10V, TA = +70°C, t<10s | 2 | ||
| Maximum Body Diode Forward Current | IS | 2.4 | A | 2 | |||
| Pulsed Drain Current | IDM | 50 | A | Note 7: repetitive, pulse width limited by junction temperature | 2 | ||
| Total Power Dissipation | PD | 1.46 | W | TA = +25°C, Note 5 | 2 | ||
| Total Power Dissipation | PD | 0.9 | W | TA = +70°C, Note 5 | 2 | ||
| Total Power Dissipation | PD | 1.7 | W | TA = +25°C, Note 6 | 2 | ||
| Total Power Dissipation | PD | 1 | W | TA = +70°C, Note 6 | 2 | ||
| Thermal Resistance, Junction to Ambient | RJA | 86 | °C/W | Steady state, Note 5 | 2 | ||
| Thermal Resistance, Junction to Ambient | RJA | 46 | °C/W | t<10s, Note 5 | 2 | ||
| Thermal Resistance, Junction to Ambient | RJA | 75 | °C/W | Steady state, Note 6 | 2 | ||
| Thermal Resistance, Junction to Ambient | RJA | 40 | °C/W | t<10s, Note 6 | 2 | ||
| Thermal Resistance, Junction to Case | RJC | 15 | °C/W | Note 6 | 2 | ||
| Operating and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 2 | ||
| Drain-Source Breakdown Voltage | BVDSS | 30 | V | VGS = 0V, ID = 250μA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 1 | μA | VDS = 30V, VGS = 0V | 2 | ||
| Gate-Source Leakage | IGSS | 100 | nA | VGS = 20V, VDS = 0V | 2 | ||
| Gate Threshold Voltage | VGS(th) | 0.8 | 1.2 | 1.6 | V | VDS = VGS, ID = 250μA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | 11 | 14 | mΩ | VGS = 10V, ID = 9A | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 14 | 20 | mΩ | VGS = 4.5V, ID = 7A | 2 | |
| Diode Forward Voltage | VSD | 0.72 | 0.94 | V | VGS = 0V, IS = 1A | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | Terminals Connections: See Diagram Terminals: Finish - Matte Tin annealed over Copper lead frame. | 1 |
CAD (KiCad official)
- Symbol:
DMN4800LSS-13 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
dmn4800lss-13-etched.step/dmn4800lss-13-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmn4800lss-13.step/dmn4800lss-13.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (6 pp, sha256
02fc8bd4320ed764, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DMN4800LSS-13
**Diodes Incorporated** · MOSFETs · SO-8
DMN4800LSS-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the N-channel MOSFET, tied to the other source pins. |
| 2 | S | passive | Source terminal of the N-channel MOSFET, tied to the other source pins. |
| 3 | S | passive | Source terminal of the N-channel MOSFET, tied to the other source pins. |
| 4 | G | input | Gate terminal; gate-source voltage is rated at 25V maximum with a threshold of 0.8V to 1.6V. |
| 5 | D | passive | Drain terminal, rated at 30V VDSS and 8.6A continuous at TA=+25°C, tied to the other drain pins. |
| 6 | D | passive | Drain terminal, rated at 30V VDSS and 8.6A continuous at TA=+25°C, tied to the other drain pins. |
| 7 | D | passive | Drain terminal, rated at 30V VDSS and 8.6A continuous at TA=+25°C, tied to the other drain pins. |
| 8 | D | passive | Drain terminal, rated at 30V VDSS and 8.6A continuous at TA=+25°C, tied to the other drain pins. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS | | | 30 | V | | 2 |
| Gate-Source Voltage | VGSS | | | 25 | V | | 2 |
| Continuous Drain Current, steady state | ID | | | 8.6 | A | VGS = 10V, TA = +25°C, steady state | 2 |
| Continuous Drain Current, steady state | ID | | | 6.3 | A | VGS = 10V, TA = +70°C, steady state | 2 |
| Continuous Drain Current, t<10s | ID | | | 11.8 | A | VGS = 10V, TA = +25°C, t<10s | 2 |
| Continuous Drain Current, t<10s | ID | | | 9 | A | VGS = 10V, TA = +70°C, t<10s | 2 |
| Maximum Body Diode Forward Current | IS | | | 2.4 | A | | 2 |
| Pulsed Drain Current | IDM | | | 50 | A | Note 7: repetitive, pulse width limited by junction temperature | 2 |
| Total Power Dissipation | PD | | | 1.46 | W | TA = +25°C, Note 5 | 2 |
| Total Power Dissipation | PD | | | 0.9 | W | TA = +70°C, Note 5 | 2 |
| Total Power Dissipation | PD | | | 1.7 | W | TA = +25°C, Note 6 | 2 |
| Total Power Dissipation | PD | | | 1 | W | TA = +70°C, Note 6 | 2 |
| Thermal Resistance, Junction to Ambient | RJA | | | 86 | °C/W | Steady state, Note 5 | 2 |
| Thermal Resistance, Junction to Ambient | RJA | | | 46 | °C/W | t<10s, Note 5 | 2 |
| Thermal Resistance, Junction to Ambient | RJA | | | 75 | °C/W | Steady state, Note 6 | 2 |
| Thermal Resistance, Junction to Ambient | RJA | | | 40 | °C/W | t<10s, Note 6 | 2 |
| Thermal Resistance, Junction to Case | RJC | | | 15 | °C/W | Note 6 | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 | | 150 | °C | | 2 |
| Drain-Source Breakdown Voltage | BVDSS | 30 | | | V | VGS = 0V, ID = 250μA | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | 1 | μA | VDS = 30V, VGS = 0V | 2 |
| Gate-Source Leakage | IGSS | | | 100 | nA | VGS = 20V, VDS = 0V | 2 |
| Gate Threshold Voltage | VGS(th) | 0.8 | 1.2 | 1.6 | V | VDS = VGS, ID = 250μA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 11 | 14 | mΩ | VGS = 10V, ID = 9A | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 14 | 20 | mΩ | VGS = 4.5V, ID = 7A | 2 |
| Diode Forward Voltage | VSD | | 0.72 | 0.94 | V | VGS = 0V, IS = 1A | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | Terminals Connections: See Diagram Terminals: Finish - Matte Tin annealed over Copper lead frame. | 1 |
## CAD (KiCad official)
- Symbol: `DMN4800LSS-13`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `dmn4800lss-13-etched.step` / `dmn4800lss-13-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmn4800lss-13.step` / `dmn4800lss-13.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Diodes Incorporated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885236336250880) (6 pp, sha256 `02fc8bd4320ed764`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dmn4800lss-13-datasheet.pdf)