# DMC62D2SV-7

**Diodes Incorporated** · MOSFETs · SOT-563

DMC62D2SV-7 from Diodes Incorporated, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of N-channel MOSFET Q1 (60V BVDSS, 480mA max ID at TA = +25°C). |
| 2 | G1 | input | Gate of N-channel MOSFET Q1 with VGSS rating of ±20V and threshold of 1.0V to 2.5V. |
| 3 | D2 | passive | Drain of P-channel MOSFET Q2 (-60V BVDSS, -320mA max ID at TA = +25°C). |
| 4 | S2 | passive | Source of P-channel MOSFET Q2 (-60V BVDSS, -320mA max ID at TA = +25°C). |
| 5 | G2 | input | Gate of P-channel MOSFET Q2 with VGSS rating of ±20V and threshold of -1V to -3V. |
| 6 | D1 | passive | Drain of N-channel MOSFET Q1 (60V BVDSS, 480mA max ID at TA = +25°C). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-563 |
| Category | Transistors/Thyristors |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage (N-ch Q1) | VDSS |  |  | 60 | V | Q1 N-channel, TA = +25°C | 2 |
| Gate-Source Voltage (N-ch Q1) | VGSS | -20 |  | 20 | V | Q1 N-channel, printed ±20 V | 2 |
| Continuous Drain Current (N-ch Q1) | ID |  |  | 480 | mA | VGS = 10V, steady state, TA = +25°C, Note 5 | 2 |
| Continuous Drain Current (N-ch Q1) | ID |  |  | 380 | mA | VGS = 10V, steady state, TA = +70°C, Note 5 | 2 |
| Maximum Body Diode Forward Current (N-ch Q1) | IS |  |  | 480 | mA | Note 5 | 2 |
| Pulsed Drain Current (N-ch Q1) | IDM |  |  | 1.3 | A | Note 5 | 2 |
| Pulsed Source Current (N-ch Q1) | ISM |  |  | 1.3 | A | Note 5 | 2 |
| Drain-Source Voltage (P-ch Q2) | VDSS |  |  | -60 | V | Q2 P-channel, TA = +25°C | 2 |
| Gate-Source Voltage (P-ch Q2) | VGSS | -20 |  | 20 | V | Q2 P-channel, printed ±20 V | 2 |
| Continuous Drain Current (P-ch Q2) | ID |  |  | -320 | mA | VGS = -10V, steady state, TA = +25°C, Note 5 | 2 |
| Continuous Drain Current (P-ch Q2) | ID |  |  | -250 | mA | VGS = -10V, steady state, TA = +70°C, Note 5 | 2 |
| Maximum Body Diode Forward Current (P-ch Q2) | IS |  |  | -320 | mA | Note 5 | 2 |
| Pulsed Drain Current (P-ch Q2) | IDM |  |  | -1 | A | Note 5 | 2 |
| Pulsed Source Current (P-ch Q2) | ISM |  |  | -1 | A | Note 5 | 2 |
| Total Power Dissipation | PD |  |  | 0.5 | W | Note 6, minimum recommended pad layout | 2 |
| Thermal Resistance, Junction to Ambient, Steady State | RθJA |  |  | 261 | °C/W | Note 6, minimum recommended pad layout | 2 |
| Total Power Dissipation | PD |  |  | 0.8 | W | Note 5, 1 inch square copper plate | 2 |
| Thermal Resistance, Junction to Ambient, Steady State | RθJA |  |  | 158 | °C/W | Note 5, 1 inch square copper plate | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 |  | 150 | °C |  | 2 |
| Drain-Source Breakdown Voltage (N-ch Q1) | BVDSS | 60 |  |  | V | VGS = 0V, ID = 250μA | 3 |
| Zero Gate Voltage Drain Current (N-ch Q1) | IDSS |  |  | 1 | µA | VDS = 60V, VGS = 0V | 3 |
| Gate-Source Leakage (N-ch Q1) | IGSS | -10 |  | 10 | µA | VGS = ±20V, VDS = 0V | 3 |
| Gate Threshold Voltage (N-ch Q1) | VGS(TH) | 1 |  | 2.5 | V | VDS = VGS, ID = 250μA | 3 |
| Static Drain-Source On-Resistance (N-ch Q1) | RDS(ON) |  |  | 1.7 | Ω | VGS = 10V, ID = 200mA | 3 |
| Static Drain-Source On-Resistance (N-ch Q1) | RDS(ON) |  |  | 3 | Ω | VGS = 4.5V, ID = 200mA | 3 |
| Diode Forward Voltage (N-ch Q1) | VSD |  |  | 1.4 | V | VGS = 0V, IS = 115mA | 3 |
| Drain-Source Breakdown Voltage (P-ch Q2) | BVDSS | -60 |  |  | V | VGS = 0V, ID = -250μA | 3 |
| Zero Gate Voltage Drain Current (P-ch Q2) | IDSS |  |  | -1 | µA | VDS = -60V, VGS = 0V | 3 |
| Gate-Source Leakage (P-ch Q2) | IGSS | -100 |  | 100 | nA | VGS = ±20V, VDS = 0V | 3 |
| Gate Threshold Voltage (P-ch Q2) | VGS(TH) | -1 |  | -3 | V | VDS = VGS, ID = -250μA | 3 |
| Static Drain-Source On-Resistance (P-ch Q2) | RDS(ON) |  |  | 4 | Ω | VGS = -10V, ID = -200mA | 3 |
| Static Drain-Source On-Resistance (P-ch Q2) | RDS(ON) |  |  | 6 | Ω | VGS = -4.5V, ID = -200mA | 3 |
| Diode Forward Voltage (P-ch Q2) | VSD |  |  | -1.4 | V | VGS = 0V, IS = -115mA | 3 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin |  Terminal Connections Indicator: See Diagram  Terminals: Finish, Matte Tin Annealed over Copper Leadframe. | 1 |

## CAD (KiCad official)

- Symbol: `DMC62D2SV-7`
- Footprint: `Package_TO_SOT_SMD:SOT-563`
- 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files: `dmc62d2sv-7-etched.step` / `dmc62d2sv-7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmc62d2sv-7.step` / `dmc62d2sv-7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Diodes Incorporated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603569360166535168) (10 pp, sha256 `d217cb759693163f`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dmc62d2sv-7-datasheet.pdf)