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DMC4050SSD-HXY

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HXY MOSFET MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DMC4050SSD-HXY

HXY MOSFET · MOSFETs · SOP-8

DMC4050SSD-HXY from HXY MOSFET, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of the N-channel MOSFET (Q1), rated VDS = 40V and ID = 7.2A at TA=25℃.
2 G1 input Gate of the N-channel MOSFET (Q1), rated VGS ±20V with VGS(th) 1.0V to 2.5V.
3 S2 passive Source of the P-channel MOSFET (Q2), rated VDS = -40V and ID = -6.5A at TA=25℃.
4 G2 input Gate of the P-channel MOSFET (Q2), rated VGS ±20V with VGS(th) -1.0V to -2.5V.
5 D2 passive Drain of the P-channel MOSFET (Q2), tied internally with pin 6; VDS = -40V max.
6 D2 passive Drain of the P-channel MOSFET (Q2), tied internally with pin 5; VDS = -40V max.
7 D1 passive Drain of the N-channel MOSFET (Q1), tied internally with pin 8; VDS = 40V max.
8 D1 passive Drain of the N-channel MOSFET (Q1), tied internally with pin 7; VDS = 40V max.

Key specifications

Parameter Value
Manufacturer HXY MOSFET
Package SOP-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
N-ch Drain-Source Voltage VDS 40 V N-Ch, TC=25℃ 1
P-ch Drain-Source Voltage VDS -40 V P-Ch, TC=25℃ 1
N-ch Gate-Source Voltage VGS -20 20 V N-Ch 1
P-ch Gate-Source Voltage VGS -20 20 V P-Ch 1
N-ch Continuous Drain Current ID 7.2 A TA=25℃, VGS@10V 1
P-ch Continuous Drain Current ID -6.5 A TA=25℃, VGS@10V 1
N-ch Continuous Drain Current ID 5.6 A TA=70℃, VGS@10V 1
P-ch Continuous Drain Current ID -5.1 A TA=70℃, VGS@10V 1
N-ch Pulsed Drain Current IDM 23 A N-Ch 1
P-ch Pulsed Drain Current IDM -22 A P-Ch 1
N-ch Single Pulse Avalanche Energy EAS 16.2 mJ N-Ch 1
P-ch Single Pulse Avalanche Energy EAS 39 mJ P-Ch 1
N-ch Avalanche Current IAS 18 A N-Ch 1
P-ch Avalanche Current IAS -28 A P-Ch 1
N-ch Total Power Dissipation PD 1.67 W TA=25℃ 1
P-ch Total Power Dissipation PD 1.67 W TA=25℃ 1
Storage Temperature Range TSTG -55 150 ℃ 1
Operating Junction Temperature Range TJ -55 150 ℃ 1
Thermal Resistance Junction-Ambient RθJA 75 ℃/W 1
Thermal Resistance Junction-Case RθJC 30 ℃/W 1
N-ch Drain-Source Breakdown Voltage BVDSS 40 V VGS=0V, ID=250uA 2
N-ch Static Drain-Source On-Resistance RDS(ON) 20 26 mΩ VGS=10V, ID=5A 2
N-ch Static Drain-Source On-Resistance RDS(ON) 28 33 mΩ VGS=4.5V, ID=4A 2
N-ch Gate Threshold Voltage VGS(th) 1 2.5 V VGS=VDS, ID=250uA 2
N-ch Drain-Source Leakage Current IDSS 1 uA VDS=32V, VGS=0V, TJ=25℃ 2
N-ch Drain-Source Leakage Current IDSS 5 uA VDS=32V, VGS=0V, TJ=55℃ 2
N-ch Gate-Source Leakage Current IGSS -100 100 nA VGS=±20V, VDS=0V 2
N-ch Continuous Source Current IS 6.1 A VG=VD=0V, Force Current 2
N-ch Pulsed Source Current ISM 23 A VG=VD=0V, Force Current 2
N-ch Diode Forward Voltage VSD 1.2 V VGS=0V, IS=1A, TJ=25℃ 2
P-ch Drain-Source Breakdown Voltage BVDSS -40 V VGS=0V, ID=-250uA 3
P-ch Static Drain-Source On-Resistance RDS(ON) 35 44 mΩ VGS=-10V, ID=-6A 3
P-ch Static Drain-Source On-Resistance RDS(ON) 55 68 mΩ VGS=-4.5V, ID=-4A 3
P-ch Gate Threshold Voltage VGS(th) -1 -2.5 V VGS=VDS, ID=-250uA 3
P-ch Drain-Source Leakage Current IDSS 1 uA VDS=-32V, VGS=0V, TJ=25℃ 3
P-ch Drain-Source Leakage Current IDSS 5 uA VDS=-32V, VGS=0V, TJ=55℃ 3
P-ch Gate-Source Leakage Current IGSS -100 100 nA VGS=±20V, VDS=0V 3
P-ch Continuous Source Current IS -6 A VG=VD=0V, Force Current 3
P-ch Pulsed Source Current ISM -22 A VG=VD=0V, Force Current 3
P-ch Diode Forward Voltage VSD -1.2 V VGS=0V, IS=-1A, TJ=25℃ 3
N-ch BVDSS Temperature Coefficient BVDSS/ΔTJ 0.034 V/℃ Reference to 25℃, ID=1mA 2
N-ch VGS(th) Temperature Coefficient ΔVGS(th) -4.56 mV/℃ 2
P-ch BVDSS Temperature Coefficient BVDSS/ΔTJ -0.02 V/℃ Reference to 25℃, ID=-1mA 3
P-ch VGS(th) Temperature Coefficient ΔVGS(th) 3.72 mV/℃ 3

CAD (KiCad official)

  • Symbol: DMC4050SSD-HXY
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: dmc4050ssd-hxy-etched.step / dmc4050ssd-hxy-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dmc4050ssd-hxy.step / dmc4050ssd-hxy.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HXY MOSFET datasheet (9 pp, sha256 f0e118cbe86f31bf, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF