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DM9162IEP

Public Made by Adom

by adom

DAVICOM Ethernet ICs, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DM9162IEP

DAVICOM · Ethernet ICs · LQFP-48(7x7)

DM9162IEP from DAVICOM, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD18 power_out Analog 1.8V regulator power output.
2 AVDD18 power_out Analog 1.8V regulator power output.
3 RX+ bidirectional Differential receive pair, receiving data from the media in TP mode and sending PECL data to the media in fiber mode.
4 RX- bidirectional Differential receive pair, receiving data from the media in TP mode and sending PECL data to the media in fiber mode.
5 AGND power_in Analog receive ground.
6 AGND power_in Analog transmit ground.
7 TX+ bidirectional Differential transmit pair, transmitting data to the media in TP mode and PECL data in fiber mode.
8 TX- bidirectional Differential transmit pair, transmitting data to the media in TP mode and PECL data in fiber mode.
9 AVDD18 power_out Analog 1.8V regulator power output.
10 PWRDWN input Asserted high forces power-down mode, and the device leaves power-down only after a hardware or software reset with PWRDWN low.
11 LED0/OP0 output LED driver output 0, which also latches OP0 at power-up/reset to set the forced or advertised operating mode per Table A.
12 LED1/OP1 output LED driver output 1, which also latches OP1 at power-up/reset to set the forced or advertised operating mode per Table A.
13 LED2/OP2 output LED driver output 2, which also latches OP2 at power-up/reset to set the forced or advertised operating mode per Table A.
14 CABLESTS/LINKSTS output Cable status when latched low at reset (1 = with cable connection) or link status when latched high (0 = with link).
15 DGND power_in Digital ground, also the QFN package ground.
16 TXER/TXD[4] input Transmit error, asserted high with TXEN to substitute HALT in 100Mbps mode, and becomes the fifth TXD data bit in bypass mode.
17 TXD[3] input Transmit data nibble bit 3, synchronous to TXCLK in 10/100Mbps nibble mode.
18 TXD[2] input Transmit data nibble bit 2, synchronous to TXCLK in 10/100Mbps nibble mode.
19 TXD[1] input Transmit data nibble bit 1, synchronous to TXCLK in 10/100Mbps nibble mode.
20 TXD[0] input Transmit data nibble bit 0, used as the serial data input in 10Mbps GPSI (7-Wired) mode.
21 TXEN input Transmit enable, active high to indicate valid nibble data on TXD[0:3].
22 TXCLK/50MCLK output Transmit clock providing the timing reference for TXEN, TXD and TXER, at 25MHz in 100Mbps, 2.5MHz in 10Mbps nibble mode, or 50MHz clock output in Reduced MII mode.
23 DVDD33 power_in Digital power.
24 MDC input Management data clock, provided by the management entity at up to 12.5MHz.
25 MDIO bidirectional Bi-directional management data, which may be driven by the station management entity or the PHY.
26 RXD[3]/PHYAD[3] output Receive data nibble bit 3 synchronous to RXCLK, also PHY address bit 3 latched at power-up reset.
27 RXD[2]/PHYAD[2] output Receive data nibble bit 2 synchronous to RXCLK, also PHY address bit 2 latched at power-up reset.
28 RXD[1]/PHYAD[1] output Receive data nibble bit 1 synchronous to RXCLK, also PHY address bit 1 latched at power-up reset.
29 RXD[0]/PHYAD[0] output Receive data nibble bit 0 synchronous to RXCLK, used as serial data output in 10Mbps GPSI mode, also PHY address bit 0 latched at power-up reset.
30 DVDD33 power_in Digital power.
31 LEDMODE input LED mode select, where 0 selects Dual-LED and 1 selects Normal LED.
32 MDINTR# bidirectional Status interrupt output asserted on link, speed or duplex change per interrupt register 21, with the output low when pulled up.
33 DGND power_in Digital ground.
34 RXCLK/10BTSER output Receive clock providing the timing reference for RXDV, RXD and RXER, at 25MHz in 100Mbps MII mode, and 10BTSER selects GPSI mode when latched low.
35 CRS/PHYAD[4] output Carrier sense, asserted high for carrier from receive or transmit activity in half-duplex mode, and also PHY address bit 4 latched at power-up reset.
36 COL/RMII output Collision detection, asserted high on collision in half-duplex mode, and selects Reduced MII when latched high at reset.
37 RXDV/TESTMODE output Receive data valid, asserted high when valid data is on RXD[0:3], and enables test mode when latched high at reset.
38 RXER/RXD[4]/RPTR output Receive error asserted high for an invalid symbol, becomes RXD[4] in bypass mode, and selects Repeater mode when latched high at reset.
39 DISMDIX input HP Auto-MDIX control, where 0 enables auto mode and 1 disables it.
40 RESET# input Active low input that initializes the DM9162.
41 VDD33 power_in Digital power for the crystal circuit.
42 XT2 input Reference clock input, connected across XT1 and XT2 for a 25MHz crystal, or used alone for a 25MHz or 50MHz oscillator depending on mode.
43 XT1 input Reference clock input, connected across XT1 and XT2 for a 25MHz crystal, or used alone for a 25MHz or 50MHz oscillator depending on mode.
44 DGND power_in Digital ground.
45 SD input Signal detect input for fiber operation.
46 AGND power_in Analog substrate ground.
47 BGRESG power_in Band gap ground.
48 BGRES output Band gap voltage reference resistor, which requires a 6.8K ohm +/- 1% resistor.

Key specifications

Parameter Value
Manufacturer DAVICOM
Package LQFP-48(7x7)
Category Interface ICs
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage DVDD -0.3 3.6 V *1 37
DC Input Voltage VIN -0.5 5.5 V *2 37
DC Output Voltage VOUT -0.3 3.6 V *2 37
Storage Temperature range TSTG -65 150 C - 37
Ambient Temperature TA -40 85 C For DM9162I 37
Lead Temperature (soldering, 10 sec.) LT 260 C - 37
Supply Voltage DVDD 3.135 3.3 3.465 V 37
Input Low Voltage (TTL inputs) VIL 0.8 V 38
Input High Voltage (TTL inputs) VIH 2 V 38
Input Low Leakage Current (TTL inputs) IIL -1 uA VIN = 0V 38
Input High Leakage Current (TTL inputs) IIH 1 uA VIN = 3.3V 38
Output Low Voltage (TTL outputs) VOL 0.4 V IOL = 4mA 38
Output High Voltage (TTL outputs) VOH 2.4 V IOH = -4mA 38
RX+/RX- Common mode Input Voltage VICM 1.8 V 100 Termination Across 38
100TX+/- Differential Output Voltage VTD100 1.9 2 2.1 V Peak to Peak 38
10TX+/- Differential Output Voltage VTD10 4.4 5 5.6 V Peak to Peak 38
100TX+/- Differential Output Current ITD100 19 20 21 mA 38
10TX+/- Differential Output Current ITD10 44 50 56 mA 38
100TX+/- Differential Rise/Fall Time tTR/F 3 5 ns 38
100TX+/- Differential Rise/Fall Time Mismatch tTM 0 0.5 ns 38
100TX+/- Differential Output Duty Cycle Distortion tTDC 0 0.5 ns 38
100TX+/- Differential Output Peak-to-Peak Jitter tT/T 0 1.4 ns 38
100TX+/- Differential Voltage Overshoot XOST 0 5 % 38
OSC Frequency OSC 24.9992 25 25.0008 MHz 30ppm 38
OSC Cycle Time tCKC 39.9988 40 40.0012 ns 30ppm 38
OSC Pulse Width High tPWH 16 20 24 ns 38
OSC Pulse Width Low tPWL 16 20 24 ns 38
RESET# Low Period t1 1 ms 39
Strap pin hold time with RESET# t2 40 ns 39
MDC Cycle Time t0 80 ns 39
MDIO Setup Before MDC t1 10 ns When OUTPUT By STA 39
MDIO Hold After MDC t2 10 ns When OUTPUT By STA 39
MDC To MDIO Output Delay t3 0 300 ns When OUTPUT By DM9162 39
Power Dissipation (supply current) 100BASE-TX PD 130 mA 3.3V 37
Power Dissipation (supply current) 10BASE-T TX PD 120 mA 3.3V 37
Power Dissipation (supply current) Auto-negotiation PD 50 mA 3.3V 37
Power Dissipation (supply current) Power Down Mode PD 8.2 mA 3.3V 37

CAD (KiCad official)

  • Symbol: DM9162IEP
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: dm9162iep-etched.step / dm9162iep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dm9162iep.step / dm9162iep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: DAVICOM datasheet (49 pp, sha256 d359c4fe603c3504, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF