component

DDTB122TC-7-F

Public Made by Adom

by adom

Diodes Incorporated Digital Transistors, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistorsddtb122tc-7-ffactory-2.0.0extractor-text

Verified DDTB122TC-7-F

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier mfr, 3 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DDTB122TC-7-F · SOT-23 · 3 pins
  • ✓copper: 3 copper pads, none touching another net
  • ✓datasheet: all 3 pin names found in the 3-page datasheet
  • ✓distributor: lcsc C460197, digikey DDTB122TC-FDITR-ND, mouser 621-DDTB122TC-7-F
  • ✓family: SOT-23
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-39k3my_5/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.1)
  • ✓pads: 3 pins = 3 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 3 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 17 kB, viewers/symbol.html 7 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ddtb122tc-7-f.kicad_sym✓ ddtb122tc-7-f.kicad_mod✓ ddtb122tc-7-f.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
ddtb122tc-7-f / README.md
History Download
Ray Publish 0.1.0 9d4e472

DDTB122TC-7-F

Diodes Incorporated · Digital Transistors · SOT-23

DDTB122TC-7-F from Diodes Incorporated, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol and footprint from KiCad-official CAD; the 3D model is generated from the datasheet's package dimensions.

Pinout

Pin Name Type Function
1 IN input Input (base, B) through built-in series resistor R1 of 0.22 kΩ nominal (R2 open on DDTB122TC); the emitter-to-base voltage (2) to (1) is limited to -5 V max (VEBO).
2 GND(+) power_in Ground/positive reference (emitter, E) of the PNP transistor, the reference for the -50 V supply voltage (3) to (2) and for the input voltage.
3 OUT output Output (collector, C) rated for a maximum supply voltage VCC of -50 V (3) to (2) and a maximum output current IC of -500 mA.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-23
Category Transistors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Collector-Base Breakdown Voltage BVCBO -50 V IC = -50μA 2
Collector-Emitter Breakdown Voltage BVCEO -40 V IC = -1mA 2
Emitter-Base Breakdown Voltage BVEBO -5 V IE = -50μA 2
Collector Cutoff Current ICBO -0.5 μA VCB = -50V 2
Emitter Cutoff Current IEBO -0.5 μA VEB = -4V 2
Collector-Emitter Saturation Voltage VCE(sat) -0.3 V IC = -50mA, IB = -2.5mA 2
DC Current Transfer Ratio hFE 100 250 600 IC = -5mA, VCE = -5V 2
Gain-Bandwidth Product fT 200 MHz VCE = -10V, IE = 5mA, f = 100MHz 2
Supply Voltage, (3) to (2) VCC -50 V TA = 25°C 1
Input Voltage, (2) to (1) VEBO (MAX) -5 V TA = 25°C 1
Output Current IC -500 mA TA = 25°C 1
Power Dissipation PD 200 mW Mounted on FR4 PC Board, TA = 25°C 1
Thermal Resistance, Junction to Ambient Air RθJA 625 °C/W Mounted on FR4 PC Board with recommended pad layout 1
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 1
Input Resistor R1 (nominal) R1 0.22 KΩ NOM; R2 open 1

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin • Terminals: Solderable per MIL-STD-202, Method 208 • Lead Free Plating (Matte Tin Finish annealed over Alloy 1

CAD (land: KiCad; 3D: generated from the datasheet)

  • Symbol: DDTB122TC-7-F
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23, generated on the KiCad land (body 1.3 x 2.9 mm, terminals on the pads, 1.0015 mm tall, datasheet A, midpoint of min and max). KiCad's stock model for this land is taller than the datasheet allows, so the model is generated from the datasheet drawing; the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
  • 3D model files: ddtb122tc-7-f-etched.step / ddtb122tc-7-f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ddtb122tc-7-f.step / ddtb122tc-7-f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (3 pp, sha256 f43085bd72dfc95f, retrieved 2026-11-13, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: land: KiCad official libraries (CC-BY-SA 4.0); 3D: generated from the datasheet's package dimensions (provenance.model_3d_generated).

Datasheet PDF