component
DAC904U
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"version": "0.1.0",
"type": "component",
"description": "Texas Instruments Digital To Analog Converters (DAC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"data acquisition",
"dac904u",
"factory-2.0.0",
"extractor-text"
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"component": {
"mpn": "DAC904U",
"manufacturer": "Texas Instruments",
"package": "SOIC-28-300mil",
"pin_count": 28,
"category": "Data Acquisition",
"subcategory": "Digital To Analog Converters (DAC)",
"datasheet": "https://www.ti.com/cn/lit/gpn/dac904",
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"lbr": "dac904u.lbr"
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"distributor_links": {
"lcsc": "C1554816",
"digikey": "2156-DAC904U-ND",
"mouser": "595-DAC904U"
},
"distributor_check": {
"checked_at": "2026-10-08T20:03:23Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "2156-DAC904U-ND",
"status": "found",
"lifecycle": "Active"
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"pn": "595-DAC904U",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "Bit 1 (D13)",
"type": "input",
"description": "Data bit 1, the MSB (D13) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."
},
{
"number": "2",
"name": "Bit 2 (D12)",
"type": "input",
"description": "Data bit 2 (D12) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."
},
{
"number": "3",
"name": "Bit 3 (D11)",
"type": "input",
"description": "Data bit 3 (D11) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."
},
{
"number": "4",
"name": "Bit 4 (D10)",
"type": "input",
"description": "Data bit 4 (D10) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."
},
{
"number": "5",
"name": "Bit 5 (D9)",
"type": "input",
"description": "Data bit 5 (D9) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."
},
{
"number": "6",
"name": "Bit 6 (D8)",
"type": "input",
"description": "Data bit 6 (D8) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."
},
{
"number": "7",
"name": "Bit 7 (D7)",
"type": "input",
"description": "Data bit 7 (D7) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."
},
{
"number": "8",
"name": "Bit 8 (D6)",
"type": "input",
"description": "Data bit 8 (D6) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."
},
{
"number": "9",
"name": "Bit 9 (D5)",
"type": "input",
"description": "Data bit 9 (D5) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."
},
{
"number": "10",
"name": "Bit 10 (D4)",
"type": "input",
"description": "Data bit 10 (D4) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."
},
{
"number": "11",
"name": "Bit 11 (D3)",
"type": "input",
"description": "Data bit 11 (D3) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."
},
{
"number": "12",
"name": "Bit 12 (D2)",
"type": "input",
"description": "Data bit 12 (D2) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."
},
{
"number": "13",
"name": "Bit 13 (D1)",
"type": "input",
"description": "Data bit 13 (D1) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."
},
{
"number": "14",
"name": "Bit 14 (D0)",
"type": "input",
"description": "Data bit 14 (D0), the LSB of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."
},
{
"number": "15",
"name": "PD",
"type": "input",
"description": "Power-down control input, active HIGH; it has an internal pull-down (about 45µA typical) and may be left unconnected if not used."
},
{
"number": "16",
"name": "INT/EXT",
"type": "input",
"description": "Reference select: internal reference when low (=0) and external reference when high (=1)."
},
{
"number": "17",
"name": "REFIN",
"type": "bidirectional",
"description": "Reference input/output; reference input compliance range is 0.1V to 1.25V, and the Applications section gives further details."
},
{
"number": "18",
"name": "FSA",
"type": "input",
"description": "Full-scale output adjust; one external resistor sets the full-scale output current over a 2mA to 20mA span while keeping the specified dynamic performance."
},
{
"number": "19",
"name": "BW",
"type": "passive",
"description": "Bandwidth/noise reduction pin; bypass with 0.1µF to +VA for optimum performance (optional)."
},
{
"number": "20",
"name": "AGND",
"type": "power_in",
"description": "Analog ground; AGND to DGND is limited to -0.3V to +0.3V per the absolute maximum ratings."
},
{
"number": "21",
"name": "IOUT",
"type": "output",
"description": "Complementary DAC current output; IOUT to AGND is limited to -1V to VA + 0.3V."
},
{
"number": "22",
"name": "IOUT",
"type": "output",
"description": "DAC current output; output compliance range is -1.0V to +1.25V, with nominal full scale of 20mA."
},
{
"number": "23",
"name": "BYP",
"type": "passive",
"description": "Bypass node; use 0.1µF to AGND."
},
{
"number": "24",
"name": "+VA",
"type": "power_in",
"description": "Analog supply voltage, 2.7V to 5.5V (absolute maximum +VA to AGND is -0.3V to +6V)."
},
{
"number": "25",
"name": "NC",
"type": "unconnected",
"description": "No internal connection."
},
{
"number": "26",
"name": "DGND",
"type": "power_in",
"description": "Digital ground."
},
{
"number": "27",
"name": "+VD",
"type": "power_in",
"description": "Digital supply voltage, 2.7V to 5.5V (absolute maximum +VD to DGND is -0.3V to +6V)."
},
{
"number": "28",
"name": "CLK",
"type": "input",
"description": "Clock input; data is latched on the rising edge, with minimum clock pulse high and low times of 3ns."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet gives the SO-28 pinout (DW package) as a single table shared with TSSOP-28; the DW pac; Pin types are KiCad ERC classes inferred from the functional descriptions. REFIN is typed bidirectio; Pin names are given as printed (Bit 1 to Bit 14) with the datasheet's D13 to D0 designations in pare"
],
"pages_sent": 8,
"cost_usd": 0.0712,
"at": "2026-10-08T20:02:57"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/dac904",
"pages": 24,
"sha256": "07f1171133bbfb0f",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 28,
"described": 28,
"cites_pages": true,
"refuses_to_fabricate": true
}
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