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DAC904U
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
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DAC904U
Texas Instruments · Digital To Analog Converters (DAC) · SOIC-28-300mil
DAC904U from Texas Instruments, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Bit 1 (D13) | input | Data bit 1, the MSB (D13) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |
| 2 | Bit 2 (D12) | input | Data bit 2 (D12) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |
| 3 | Bit 3 (D11) | input | Data bit 3 (D11) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |
| 4 | Bit 4 (D10) | input | Data bit 4 (D10) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |
| 5 | Bit 5 (D9) | input | Data bit 5 (D9) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |
| 6 | Bit 6 (D8) | input | Data bit 6 (D8) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |
| 7 | Bit 7 (D7) | input | Data bit 7 (D7) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |
| 8 | Bit 8 (D6) | input | Data bit 8 (D6) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |
| 9 | Bit 9 (D5) | input | Data bit 9 (D5) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |
| 10 | Bit 10 (D4) | input | Data bit 10 (D4) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |
| 11 | Bit 11 (D3) | input | Data bit 11 (D3) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |
| 12 | Bit 12 (D2) | input | Data bit 12 (D2) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |
| 13 | Bit 13 (D1) | input | Data bit 13 (D1) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |
| 14 | Bit 14 (D0) | input | Data bit 14 (D0), the LSB of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |
| 15 | PD | input | Power-down control input, active HIGH; it has an internal pull-down (about 45µA typical) and may be left unconnected if not used. |
| 16 | INT/EXT | input | Reference select: internal reference when low (=0) and external reference when high (=1). |
| 17 | REFIN | bidirectional | Reference input/output; reference input compliance range is 0.1V to 1.25V, and the Applications section gives further details. |
| 18 | FSA | input | Full-scale output adjust; one external resistor sets the full-scale output current over a 2mA to 20mA span while keeping the specified dynamic performance. |
| 19 | BW | passive | Bandwidth/noise reduction pin; bypass with 0.1µF to +VA for optimum performance (optional). |
| 20 | AGND | power_in | Analog ground; AGND to DGND is limited to -0.3V to +0.3V per the absolute maximum ratings. |
| 21 | IOUT | output | Complementary DAC current output; IOUT to AGND is limited to -1V to VA + 0.3V. |
| 22 | IOUT | output | DAC current output; output compliance range is -1.0V to +1.25V, with nominal full scale of 20mA. |
| 23 | BYP | passive | Bypass node; use 0.1µF to AGND. |
| 24 | +VA | power_in | Analog supply voltage, 2.7V to 5.5V (absolute maximum +VA to AGND is -0.3V to +6V). |
| 25 | NC | unconnected | No internal connection. |
| 26 | DGND | power_in | Digital ground. |
| 27 | +VD | power_in | Digital supply voltage, 2.7V to 5.5V (absolute maximum +VD to DGND is -0.3V to +6V). |
| 28 | CLK | input | Clock input; data is latched on the rising edge, with minimum clock pulse high and low times of 3ns. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-28-300mil |
| Category | Data Acquisition |
| Pins | 28 |
CAD (KiCad official)
- Symbol:
DAC904U - Footprint:
Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm - 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
- 3D model files:
dac904u-etched.step/dac904u-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac904u.step/dac904u.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (24 pp, sha256
07f1171133bbfb0f, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).