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DAC8814ICDBR

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Texas Instruments Digital To Analog Converters (DACs), SSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersdac8814icdbrfactory-2.0.0extractor-text

Verified DAC8814ICDBR

by Ray · last 13 Nov 2026 · 2 records · files match
SymbolFootprint3D modelPins

Verification log 2 records

13 Nov 2026RayRebuilt by the parts factory: tier mfr, 28 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DAC8814ICDBR · SSOP-28 · 28 pins
  • ✓copper: 28 copper pads, none touching another net
  • ✓datasheet: all 28 pin names found in the 30-page datasheet
  • ✓distributor: lcsc C2877450, digikey DAC8814ICDBR-ND, mouser 595-DAC8814ICDBR
  • ✓family: SSOP-28_5.3x10.2mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-jdixtxwn/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.27)
  • ✓pads: 28 pins = 28 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 28 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 44 kB, viewers/symbol.html 21 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dac8814icdbr.kicad_sym✓ dac8814icdbr.kicad_mod✓ dac8814icdbr.step
12 Nov 2026RayPublished by the parts factory: tier mfr, 28 pinsre-verified
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DAC8814ICDBR · SSOP-28 · 28 pins
  • ✓copper: 28 copper pads, none touching another net
  • ✓datasheet: all 28 pin names found in the 30-page datasheet
  • ✓distributor: lcsc C2877450, digikey DAC8814ICDBR-ND, mouser 595-DAC8814ICDBR
  • ✓family: SSOP-28_5.3x10.2mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-fwbsetx3/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.27)
  • ✓pads: 28 pins = 28 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 28 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 44 kB, viewers/symbol.html 21 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files! dac8814icdbr.kicad_sym✓ dac8814icdbr.kicad_mod✓ dac8814icdbr.step
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Ray Publish 0.1.2 b73af72

DAC8814ICDBR

Texas Instruments · Digital To Analog Converters (DACs) · SSOP-28

DAC8814ICDBR from Texas Instruments, in a SSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGNDA power_in DAC A analog ground; AGNDX should be Kelvin-connected to the load point in the circuit requiring full 16-bit accuracy.
2 IOUTA output DAC A current output, connected to the inverting input of the external I-to-V amplifier; output current is 1.6 mA min and 2.5 mA max at code FFFFh.
3 VREFA input DAC A reference voltage input that sets full-scale output voltage; specified range is -15 V to +15 V and it can be tied to VDD.
4 RFBA input DAC A feedback resistor terminal that establishes the output voltage when connected to the external amplifier output.
5 MSB input Sets the reset code during an RS pulse or at power-on: tied to ground selects zero-code, tied to VDD selects half-scale (8000h).
6 RS input Active-low reset that forces the input and DAC registers to zero or 8000h as determined by the MSB pin voltage.
7 VDD power_in Positive power-supply input; specified operating range is +2.7 V to +5.5 V.
8 CS input Active-low chip select that disables shift-register loading when high and transfers shift-register data to the input register on its rising edge.
9 CLK input Clock input; data is clocked into the shift register on the positive edge, with a maximum clock frequency of 50 MHz.
10 SDI input Serial data input; data loads directly into the shift register.
11 RFBB input DAC B feedback resistor terminal that establishes the output voltage when connected to the external amplifier output.
12 VREFB input DAC B reference voltage input that sets full-scale output voltage; specified range is -15 V to +15 V and it can be tied to VDD.
13 IOUTB output DAC B current output, connected to the inverting input of the external I-to-V amplifier; output current is 1.6 mA min and 2.5 mA max at code FFFFh.
14 AGNDB power_in DAC B analog ground; AGNDX should be Kelvin-connected to the load point in the circuit requiring full 16-bit accuracy.
15 AGNDC power_in DAC C analog ground; AGNDX should be Kelvin-connected to the load point in the circuit requiring full 16-bit accuracy.
16 IOUTC output DAC C current output, connected to the inverting input of the external I-to-V amplifier; output current is 1.6 mA min and 2.5 mA max at code FFFFh.
17 VREFC input DAC C reference voltage input that sets full-scale output voltage; specified range is -15 V to +15 V and it can be tied to VDD.
18 RFBC input DAC C feedback resistor terminal that establishes the output voltage when connected to the external amplifier output.
19 NC unconnected Not connected internally; leave floating.
20 SDO output Serial data output that presents input data 19 clock pulses after it is applied at SDI, allowing daisy-chaining of packages.
21 LDAC input Level-sensitive active-low load DAC strobe that asynchronously transfers all input-register data to the DAC registers; minimum pulse width 25 ns.
22 AGNDF power_in High-current analog force ground.
23 VSS power_in Datasheet states no internal connection for this pin.
24 DGND power_in Digital ground.
25 RFBD input DAC D feedback resistor terminal that establishes the output voltage when connected to the external amplifier output.
26 VREFD input DAC D reference voltage input that sets full-scale output voltage; specified range is -15 V to +15 V and it can be tied to VDD.
27 IOUTD output DAC D current output, connected to the inverting input of the external I-to-V amplifier; output current is 1.6 mA min and 2.5 mA max at code FFFFh.
28 AGNDD power_in DAC D analog ground; AGNDX should be Kelvin-connected to the load point in the circuit requiring full 16-bit accuracy.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-28
Category Data Converters
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply range VDD 2.7 5.5 V 4
Relative accuracy (INL), DAC8814C INL -1 1 LSB 3
Differential nonlinearity (DNL), DAC8814C DNL -1 1 LSB 3
Output leakage current IOUTX 10 nA Data = 0000h, TA = 25°C 3
Output leakage current IOUTX 20 nA Data = 0000h, TA = TA max 3
Full-scale gain error GFSE -3 0.75 3 mV Data = FFFFh 3
Full-scale tempco TCVFS 1 ppm/°C 3
Reference input voltage range VREFX -15 15 V 3
Reference input resistance RREFX 4 5 6 kΩ 3
Reference input resistance match RREFX 1 % Channel-to-channel 3
Feedback resistor RFBX 5 kΩ VDD = 5 V 3
Reference input capacitance CREFX 5 pF 3
Output current IOUTX 1.6 2.5 mA Data = FFFFh 3
Output capacitance COUTX 50 pF Code-dependent 3
Input low voltage VIL 0.6 V VDD = +2.7 V 3
Input low voltage VIL 0.8 V VDD = +5 V 3
Input high voltage VIH 2.1 V VDD = +2.7 V 3
Input high voltage VIH 2.4 V VDD = +5 V 3
Input capacitance CIL 10 pF 3
Logic output low voltage VOL 0.4 V IOL = 1.6 mA 3
Logic output high voltage VOH 4 V IOH = 100 µA 3
Clock input frequency fCLK 50 MHz 3
Clock width high tCH 10 ns 3
Clock width low tCL 10 ns 3
CS to clock setup tCSS 0 ns 3
Clock to CS hold tCSH 10 ns 3
Clock to SDO propagation delay tPD 2 20 ns 3
Load DAC pulsewidth tLDAC 25 ns 3
Data setup tDS 5 ns 3
Data hold tDH 10 ns 3
Load setup tLDS 5 ns 3
Load hold tLDH 10 ns 3
Positive supply current IDD 2 5 µA Logic inputs = 0 V, VDD = +4.5 V to +5.5 V 4
Positive supply current IDD 1 2.5 µA Logic inputs = 0 V, VDD = +2.7 V to +3.6 V 4
Output voltage settling time ts 0.3 µs To ±0.1% of full-scale, Data = 0000h to FFFFh to 0000h 4
Output voltage settling time ts 0.5 µs To ±0.0015% of full-scale, Data = 0000h to FFFFh to 0000h 4
VDD to GND VDD -0.3 8 V 2
VREF to GND VREF -18 18 V 2
Logic inputs and output to GND -0.3 8 V 2
V(IOUT) to GND V(IOUT) -0.3 V 2
AGNDX to DGND -0.3 0.3 V 2
Input current to any pin except supplies -50 50 mA 2
Thermal resistance, junction-to-ambient θJA 100 °C/W 28-Lead shrink surface-mount (RS-28) 2
Maximum junction temperature TJmax 150 °C 2
Operating temperature range, Model A TA -40 85 °C 2
Storage temperature range Tstg -65 150 °C 2
ESD rating, HBM 3000 V 2
ESD rating, CDM 500 V 2

CAD (KiCad official)

  • Symbol: DAC8814ICDBR
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28 (KiCad packages3D, STEP)
  • 3D model files: dac8814icdbr-etched.step / dac8814icdbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac8814icdbr.step / dac8814icdbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 ac0123b387c7c750, retrieved 2026-11-13, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF