component
DAC8562TDGST
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), VSSOP-10-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
DAC8562TDGST
Texas Instruments · Digital To Analog Converters (DAC) · VSSOP-10-0.5mm
DAC8562TDGST from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC-A |
| 2 | VOUTB | output | Analog output voltage from DAC-B |
| 3 | GND | power_in | Ground reference point for all circuitry on the device |
| 4 | LDAC | input | Negative edge-triggered timing signal for simultaneous DAC updates in asynchronous mode; must be connected to GND or held low before sending commands in synchronous mode |
| 5 | CLR | input | Falling-edge-sensitive asynchronous clear input; loads zero scale (DACxx62T) or mid-scale (DACxx63T) to all input and DAC registers |
| 6 | SYNC | input | Level-triggered active-low frame synchronization signal for input data; Schmitt-trigger logic input |
| 7 | SCLK | input | Serial clock input for data transfer up to 50 MHz; Schmitt-trigger logic input |
| 8 | DIN | input | Serial data input clocked into 24-bit shift register on each falling edge of SCLK; Schmitt-trigger logic input |
| 9 | AVDD | power_in | Power-supply input voltage from 2.7 V to 5.5 V |
| 10 | VREFIN/VREFOUT | bidirectional | Bidirectional voltage reference pin; provides 2.5-V output when internal reference is used or accepts external reference input |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | Data Acquisition |
| Pins | 10 |
CAD (KiCad official)
- Symbol:
DAC8562TDGST - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files:
dac8562tdgst-etched.step/dac8562tdgst-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac8562tdgst.step/dac8562tdgst.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (63 pp, sha256
c924f9150c60d73e, retrieved 2026-10-03, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DAC8562TDGST
**Texas Instruments** · Digital To Analog Converters (DAC) · VSSOP-10-0.5mm
DAC8562TDGST from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC-A |
| 2 | VOUTB | output | Analog output voltage from DAC-B |
| 3 | GND | power_in | Ground reference point for all circuitry on the device |
| 4 | LDAC | input | Negative edge-triggered timing signal for simultaneous DAC updates in asynchronous mode; must be connected to GND or held low before sending commands in synchronous mode |
| 5 | CLR | input | Falling-edge-sensitive asynchronous clear input; loads zero scale (DACxx62T) or mid-scale (DACxx63T) to all input and DAC registers |
| 6 | SYNC | input | Level-triggered active-low frame synchronization signal for input data; Schmitt-trigger logic input |
| 7 | SCLK | input | Serial clock input for data transfer up to 50 MHz; Schmitt-trigger logic input |
| 8 | DIN | input | Serial data input clocked into 24-bit shift register on each falling edge of SCLK; Schmitt-trigger logic input |
| 9 | AVDD | power_in | Power-supply input voltage from 2.7 V to 5.5 V |
| 10 | VREFIN/VREFOUT | bidirectional | Bidirectional voltage reference pin; provides 2.5-V output when internal reference is used or accepts external reference input |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | Data Acquisition |
| Pins | 10 |
## CAD (KiCad official)
- Symbol: `DAC8562TDGST`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files: `dac8562tdgst-etched.step` / `dac8562tdgst-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac8562tdgst.step` / `dac8562tdgst.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac8162t) (63 pp, sha256 `c924f9150c60d73e`, retrieved 2026-10-03, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dac8562tdgst-datasheet.pdf)