component
DAC8562TDGSR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), VSSOP-10-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"category": "ADC/DAC/Data Conversion",
"subcategory": "Digital To Analog Converters (DACs)",
"datasheet": "https://www.ti.com/cn/lit/gpn/dac8162t",
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"digikey": "296-DAC8562TDGSRTR-ND",
"mouser": "595-DAC8562TDGSR"
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"pins": [
{
"number": "1",
"name": "VOUTA",
"type": "output",
"description": "Analog output voltage from DAC-A; the datasheet's absolute maximum for VOUT[A, B] to GND is -0.3 V to AVDD + 0.3 V."
},
{
"number": "2",
"name": "VOUTB",
"type": "output",
"description": "Analog output voltage from DAC-B; the datasheet's absolute maximum for VOUT[A, B] to GND is -0.3 V to AVDD + 0.3 V."
},
{
"number": "3",
"name": "GND",
"type": "power_in",
"description": "Ground reference point for all circuitry on the device."
},
{
"number": "4",
"name": "LDAC",
"type": "input",
"description": "Load-DAC input: in asynchronous mode a negative edge updates all DAC outputs simultaneously and LDAC must return high before the next serial command, while in synchronous mode it must be tied to GND permanently or held low before commands are sent."
},
{
"number": "5",
"name": "CLR",
"type": "input",
"description": "Falling-edge-sensitive asynchronous clear input that loads the zero-scale value into all input and DAC registers on the DAC8562T, and the device exits clear mode on the 24th falling edge of the next write."
},
{
"number": "6",
"name": "SYNC",
"type": "input",
"description": "Level-triggered active-low frame sync input (Schmitt-trigger); the DAC output updates after the 24th falling SCLK edge, and a SYNC rising edge before the 23rd clock edge interrupts and discards the write."
},
{
"number": "7",
"name": "SCLK",
"type": "input",
"description": "Serial clock input (Schmitt-trigger) with data transfer rates of up to 50 MHz."
},
{
"number": "8",
"name": "DIN",
"type": "input",
"description": "Serial data input (Schmitt-trigger) clocked into the 24-bit input shift register on each falling edge of SCLK."
},
{
"number": "9",
"name": "AVDD",
"type": "power_in",
"description": "Power-supply input with a recommended range of 2.7 V to 5.5 V."
},
{
"number": "10",
"name": "VREFIN/VREFOUT",
"type": "bidirectional",
"description": "Bidirectional voltage reference pin that provides a 2.5-V output when the internal reference is used, and otherwise accepts a reference input from 0 V to AVDD."
}
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"primary_model": "claude-haiku-5-5",
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"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet pin table covers both the VSSOP (DGS) and WSON (DSC) packages. The pin numbers above a; The top-view drawing for the DGS package shows a 'Thermal Pad(1)' label, but the DGS column in the t; The CLR description reflects the DAC8562T's zero-scale clear value from Table 10 on page 34, not the"
],
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"cost_usd": 0.079,
"at": "2026-10-11T20:58:58"
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"sha256": "c924f9150c60d73e",
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"metadata": {
"specs": {
"Manufacturer": "Texas Instruments",
"Package": "VSSOP-10-0.5mm",
"Category": "ADC/DAC/Data Conversion",
"Pins": "10"
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