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DAC8562TDGSR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), VSSOP-10-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDAC8562TDGSR
Texas Instruments · Digital To Analog Converters (DACs) · VSSOP-10-0.5mm
DAC8562TDGSR from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC-A; the datasheet's absolute maximum for VOUT[A, B] to GND is -0.3 V to AVDD + 0.3 V. |
| 2 | VOUTB | output | Analog output voltage from DAC-B; the datasheet's absolute maximum for VOUT[A, B] to GND is -0.3 V to AVDD + 0.3 V. |
| 3 | GND | power_in | Ground reference point for all circuitry on the device. |
| 4 | LDAC | input | Load-DAC input: in asynchronous mode a negative edge updates all DAC outputs simultaneously and LDAC must return high before the next serial command, while in synchronous mode it must be tied to GND permanently or held low before commands are sent. |
| 5 | CLR | input | Falling-edge-sensitive asynchronous clear input that loads the zero-scale value into all input and DAC registers on the DAC8562T, and the device exits clear mode on the 24th falling edge of the next write. |
| 6 | SYNC | input | Level-triggered active-low frame sync input (Schmitt-trigger); the DAC output updates after the 24th falling SCLK edge, and a SYNC rising edge before the 23rd clock edge interrupts and discards the write. |
| 7 | SCLK | input | Serial clock input (Schmitt-trigger) with data transfer rates of up to 50 MHz. |
| 8 | DIN | input | Serial data input (Schmitt-trigger) clocked into the 24-bit input shift register on each falling edge of SCLK. |
| 9 | AVDD | power_in | Power-supply input with a recommended range of 2.7 V to 5.5 V. |
| 10 | VREFIN/VREFOUT | bidirectional | Bidirectional voltage reference pin that provides a 2.5-V output when the internal reference is used, and otherwise accepts a reference input from 0 V to AVDD. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |
CAD (KiCad official)
- Symbol:
DAC8562TDGSR - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files:
dac8562tdgsr-etched.step/dac8562tdgsr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac8562tdgsr.step/dac8562tdgsr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (63 pp, sha256
c924f9150c60d73e, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).