DAC8560IADGKR

{
  "slug": "dac8560iadgkr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Digital To Analog Converters (DAC), VSSOP-8-0.65mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "data acquisition",
    "dac8560iadgkr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
  },
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    "README.md",
    "dac8560iadgkr.kicad_sym",
    "dac8560iadgkr.kicad_mod",
    "dac8560iadgkr.glb",
    "dac8560iadgkr.step",
    "dac8560iadgkr.lbr",
    "docs/hero.png",
    "docs/dac8560iadgkr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "dac8560iadgkr-hero.glb",
    "dac8560iadgkr-hero.overlay.json",
    "dac8560iadgkr-etched.glb"
  ],
  "component": {
    "mpn": "DAC8560IADGKR",
    "manufacturer": "Texas Instruments",
    "package": "VSSOP-8-0.65mm",
    "pin_count": 8,
    "category": "Data Acquisition",
    "subcategory": "Digital To Analog Converters (DAC)",
    "datasheet": "https://www.ti.com.cn/cn/lit/ds/symlink/dac8560.pdf?ts=1739430651866&ref_url=https%253A%252F%252Fwww.ti.com.cn%252Fsitesearch%252Fzh-cn%252Fdocs%252Funiversalsearch.tsp%253FlangPref%253Dzh-CN%2526nr%253D10%2526searchTerm%253DDAC8560IADGKR",
    "parts": {
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      "footprint": "dac8560iadgkr.kicad_mod",
      "model_3d": "dac8560iadgkr-hero.glb",
      "model_3d_plain": "dac8560iadgkr-etched.glb",
      "model_3d_step": "dac8560iadgkr-etched.step",
      "model_3d_step_plain": "dac8560iadgkr.step",
      "lbr": "dac8560iadgkr.lbr"
    },
    "distributor_links": {
      "lcsc": "C169581",
      "digikey": "296-49165-2-ND",
      "mouser": "595-DAC8560IADGKR"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T00:46:14Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-49165-2-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "595-DAC8560IADGKR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply input, 2.7 V to 5.5 V (VDD to GND)."
      },
      {
        "number": "2",
        "name": "VREF",
        "type": "power_in",
        "description": "Reference voltage input/output for the DAC; the internal 2.5 V reference is enabled by default and can source up to 20 mA at this pin."
      },
      {
        "number": "3",
        "name": "VFB",
        "type": "input",
        "description": "Feedback connection for the output amplifier; for voltage output operation it must be tied externally to VOUT."
      },
      {
        "number": "4",
        "name": "VOUT",
        "type": "output",
        "description": "Analog output voltage from the DAC, driven by an output amplifier with rail-to-rail operation."
      },
      {
        "number": "5",
        "name": "SYNC",
        "type": "input",
        "description": "Active-LOW, level-triggered frame sync input with Schmitt-trigger logic; data is sampled on subsequent falling SCLK edges and the DAC updates after the 24th clock, and a SYNC rising edge before the 24th clock causes the write to be ignored."
      },
      {
        "number": "6",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input with Schmitt-trigger logic."
      },
      {
        "number": "7",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input, clocked into the 24-bit input shift register on each falling SCLK edge, with Schmitt-trigger logic."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference point for all circuitry on the device."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin table on page 3 is for the DGK (8-pin VSSOP) package only; the packaging addendum on page 34; The datasheet pin table gives I/O direction 'I/O' for VREF, mapped to KiCad 'bidirectional'. Verify "
        ],
        "pages_sent": 8,
        "cost_usd": 0.0464,
        "at": "2026-10-18T00:44:18"
      },
      "datasheet": {
        "url": "https://www.ti.com.cn/cn/lit/ds/symlink/dac8560.pdf?ts=1739430651866&ref_url=https%253A%252F%252Fwww.ti.com.cn%252Fsitesearch%252Fzh-cn%252Fdocs%252Funiversalsearch.tsp%253FlangPref%253Dzh-CN%2526nr%253D10%2526searchTerm%253DDAC8560IADGKR",
        "pages": 41,
        "sha256": "22f6d2eb0c9480a8",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
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        "footprint_binding": "identity",
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        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
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  }
}