main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers dac8560iadgkr: viewers · Ray 8d ago
dac8560iadgkr-etched.glb Publish 0.1.0 · Ray 8d ago
dac8560iadgkr-etched.step dac8560iadgkr: factory component page (tier=lcsc) · Ray 8d ago
dac8560iadgkr-hero.glb dac8560iadgkr: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
dac8560iadgkr-hero.overlay.json Publish 0.1.0 · Ray 8d ago
dac8560iadgkr.glb Publish 0.1.0 · Ray 8d ago
dac8560iadgkr.kicad_mod Publish 0.1.0 · Ray 8d ago
dac8560iadgkr.kicad_sym Publish 0.1.0 · Ray 8d ago
dac8560iadgkr.lbr Publish 0.1.0 · Ray 8d ago
dac8560iadgkr.step Publish 0.1.0 · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago

DAC8560IADGKR

Texas Instruments · Digital To Analog Converters (DAC) · VSSOP-8-0.65mm

DAC8560IADGKR from Texas Instruments, in a VSSOP-8-0.65mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply input, 2.7 V to 5.5 V (VDD to GND).
2 VREF power_in Reference voltage input/output for the DAC; the internal 2.5 V reference is enabled by default and can source up to 20 mA at this pin.
3 VFB input Feedback connection for the output amplifier; for voltage output operation it must be tied externally to VOUT.
4 VOUT output Analog output voltage from the DAC, driven by an output amplifier with rail-to-rail operation.
5 SYNC input Active-LOW, level-triggered frame sync input with Schmitt-trigger logic; data is sampled on subsequent falling SCLK edges and the DAC updates after the 24th clock, and a SYNC rising edge before the 24th clock causes the write to be ignored.
6 SCLK input Serial clock input with Schmitt-trigger logic.
7 DIN input Serial data input, clocked into the 24-bit input shift register on each falling SCLK edge, with Schmitt-trigger logic.
8 GND power_in Ground reference point for all circuitry on the device.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VSSOP-8-0.65mm
Category Data Acquisition
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative accuracy (DAC8560A grade) -12 4 12 LSB Measured by line passing through codes 485 and 64714 5
Differential nonlinearity -1 0.5 1 LSB 16-bit Monotonic 5
Zero-code error -12 5 12 mV Measured by line passing through codes 485 and 64714. 5
Full-scale error -0.5 0.2 0.5 % of FSR 5
Gain error -0.2 0.05 0.2 % of FSR 5
Output voltage range 0 V 5
Output voltage settling time 8 10 μs To ±0.003% FSR, 0200h to FD00h, RL = 2 kΩ, 0 pF < CL < 200 pF 5
Output voltage 2.4975 2.5 2.5025 V TA = 25°C 6
Initial accuracy -0.1 0.004 0.1 % TA = 25°C 6
Output voltage temperature drift (DAC8560A, DAC8560B) 5 25 ppm/°C 6
Reference input range 0 V 6
Input current -1 1 μA 6
Output current load capability -20 20 mA 6
Supply voltage VDD 2.7 5.5 V 6
Normal mode supply current IDD 0.53 0.85 mA VDD = 3.6 V to 5.5 V, VIH = VDD and VIL = GND 6
Normal mode supply current IDD 0.51 0.84 mA VDD = 2.7 V to 3.6 V, VIH = VDD and VIL = GND 6
All power-down modes supply current IDD 1.2 2.5 μA VDD = 3.6 V to 5.5 V, VIH = VDD and VIL = GND 6
All power-down modes supply current IDD 0.7 2.2 μA VDD = 2.7 V to 3.6 V, VIH = VDD and VIL = GND 6
Normal mode power dissipation 2.6 4.7 mW VDD = 3.6 V to 5.5 V 6
Normal mode power dissipation 1.5 3 mW VDD = 2.7 V to 3.6 V 6
All power-down modes power dissipation 6 14 μW VDD = 3.6 V to 5.5 V 6
All power-down modes power dissipation 2 8 μW VDD = 2.7 V to 3.6 V 6
Specified performance temperature range -40 105 °C 6
Supply voltage (VDD to GND) VDD 2.7 5.5 V 4
Digital input voltage (DIN, SCLK, SYNC) 0 V 4
Operating ambient temperature TA -40 125 °C 4
VDD to GND VDD -0.3 6 V 4
Digital input voltage to GND -0.3 V 4
VOUT to GND VOUT -0.3 V 4
Operating temperature -40 105 °C 4
Junction temperature TJ(MAX) 150 °C 4
Storage temperature Tstg -65 150 °C 4
Electrostatic discharge, human-body model (HBM) V(ESD) -4000 4000 V Per ANSI/ESDA/JEDEC JS-001 4
Electrostatic discharge, charged-device model (CDM) V(ESD) -1500 1500 V Per JEDEC specification JESD22-C101 4
Junction-to-ambient thermal resistance (DGK, 8 pins) RθJA 206 °C/W 4
Junction-to-case (top) thermal resistance (DGK, 8 pins) RθJC(top) 44 °C/W 4
Junction-to-board thermal resistance (DGK, 8 pins) RθJB 94.2 °C/W 4
Junction-to-top characterization parameter (DGK, 8 pins) ψJT 10.2 °C/W 4
Junction-to-board characterization parameter (DGK, 8 pins) ψJB 92.7 °C/W 4

CAD (KiCad official)

  • Symbol: DAC8560IADGKR
  • Footprint: Package_SO:VSSOP-8_2.3x2mm_P0.5mm
  • 3D model: VSSOP-8-0.65mm (KiCad packages3D, STEP)
  • 3D model files: dac8560iadgkr-etched.step / dac8560iadgkr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac8560iadgkr.step / dac8560iadgkr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 22f6d2eb0c9480a8, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF