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DAC8311IDCKT

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Texas Instruments Digital To Analog Converters (DACs), SC-70-6(SOT-363). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs dac8311idckt: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers dac8311idckt: viewers · Ray 1mo ago
dac8311idckt-etched.fit.json dac8311idckt: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
dac8311idckt-etched.glb dac8311idckt: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
dac8311idckt-etched.step dac8311idckt: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
dac8311idckt.glb Publish 0.1.0 · Ray 1mo ago
dac8311idckt.kicad_mod Publish 0.1.0 · Ray 1mo ago
dac8311idckt.kicad_sym Publish 0.1.0 · Ray 1mo ago
dac8311idckt.lbr Publish 0.1.0 · Ray 1mo ago
dac8311idckt.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json dac8311idckt: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md dac8311idckt: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

DAC8311IDCKT

Texas Instruments · Digital To Analog Converters (DACs) · SC-70-6(SOT-363)

DAC8311IDCKT from Texas Instruments, in a SC-70-6(SOT-363). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SYNC input Active-low, level-triggered frame synchronization input for the serial interface. When SYNC goes low, the input shift register is enabled and data is clocked in on the falling edges of SCLK; the DAC is updated after the 16th clock cycle unless SYNC is taken high early (in which case the rising edge acts as an interrupt and the write is ignored).
2 SCLK input Serial clock input. Data on DIN is clocked into the shift register on the falling edge of SCLK at rates up to 50 MHz. Schmitt-triggered logic input.
3 DIN input Serial data input. Data is clocked into the 16-bit (DAC8311) input shift register on the falling edge of SCLK while SYNC is low.
4 AVDD/VREF power_in Analog power supply input and reference voltage for the DAC, +2 V to +5.5 V. AVDD sets the full-scale output range (VOUT = 0 to AVDD). Decouple to GND with appropriate bypass capacitors.
5 GND power_in Ground reference for all analog and digital circuitry on the device.
6 VOUT output Analog voltage output from the DAC. The rail-to-rail output amplifier swings from 0 V to AVDD and can drive a 2 kΩ load with up to 200 pF capacitance while maintaining stability.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SC-70-6(SOT-363)
Category ADC/DAC/Data Conversion
Pins 6

Ordering variants

Same part, different packaging or reel option.

  • DAC8311IDCKT
  • DAC8311IDCKR

CAD (KiCad official)

  • Symbol: DAC8311IDCKT
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SC-70-6(SOT-363) (KiCad packages3D, STEP)
  • 3D model files: dac8311idckt-etched.step / dac8311idckt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac8311idckt.step / dac8311idckt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 8453ec6a1673f061, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF