component
DAC8163TDSCR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), WSON-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"component": {
"mpn": "DAC8163TDSCR",
"manufacturer": "Texas Instruments",
"package": "WSON-10-EP(3x3)",
"pin_count": 11,
"category": "Data Acquisition",
"subcategory": "Digital To Analog Converters (DAC)",
"datasheet": "https://www.ti.com/cn/lit/gpn/dac8162t",
"parts": {
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"distributor_links": {
"lcsc": "C2869611",
"digikey": "296-43257-2-ND",
"mouser": "595-DAC8163TDSCR"
},
"distributor_check": {
"checked_at": "2026-10-11T01:20:16Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "296-43257-2-ND",
"status": "found",
"lifecycle": "Active"
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"pins": [
{
"number": "1",
"name": "VOUTA",
"type": "output",
"description": "Analog output voltage from DAC-A."
},
{
"number": "2",
"name": "VOUTB",
"type": "output",
"description": "Analog output voltage from DAC-B."
},
{
"number": "3",
"name": "GND",
"type": "power_in",
"description": "Ground reference point for all circuitry on the device."
},
{
"number": "4",
"name": "LDAC",
"type": "input",
"description": "Must be connected to GND permanently or held low before commands are sent in synchronous mode; in asynchronous mode a negative edge updates all DAC output registers simultaneously, and LDAC must return high before the next serial command."
},
{
"number": "5",
"name": "CLR",
"type": "input",
"description": "Falling-edge-sensitive asynchronous clear input that loads mid-scale (DACxx63T) into all input and DAC registers, and activating it during a write sequence aborts that write."
},
{
"number": "6",
"name": "SYNC",
"type": "input",
"description": "Active-low level-triggered frame synchronization input; a rising edge before the 23rd clock edge acts as an interrupt that discards the write sequence, and the DAC updates on the 24th falling SCLK edge."
},
{
"number": "7",
"name": "SCLK",
"type": "input",
"description": "Serial clock input supporting data transfer at rates up to 50 MHz, with Schmitt-trigger logic input."
},
{
"number": "8",
"name": "DIN",
"type": "input",
"description": "Serial data input clocked into the 24-bit input shift register on each falling SCLK edge, with Schmitt-trigger logic input."
},
{
"number": "9",
"name": "AVDD",
"type": "power_in",
"description": "Power-supply input specified at 2.7 V to 5.5 V (AVDD to GND, absolute maximum 6 V)."
},
{
"number": "10",
"name": "VREFIN/VREFOUT",
"type": "bidirectional",
"description": "Bidirectional voltage reference pin that provides a 2.5-V output when the internal reference is used, and otherwise accepts an external reference of 0 V to AVDD."
},
{
"number": "11",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
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"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
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"exposed pad 11 added from the footprint"
],
"pages_sent": 13,
"cost_usd": 0.0854,
"at": "2026-10-11T01:19:59"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/dac8162t",
"pages": 63,
"sha256": "c924f9150c60d73e",
"source_tier": "lcsc"
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