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DAC7565ICPWR
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Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# DAC7565ICPWR++**Texas Instruments** · Digital To Analog Converters (DAC) · TSSOP-16++DAC7565ICPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VOUTA | output | Analog output voltage from DAC A. |+| 2 | VOUTB | output | Analog output voltage from DAC B. |+| 3 | VREFH/VREFOUT | bidirectional | Positive reference input, or reference output at 2.5V when the internal reference is used; the internal reference can source up to 20mA at this pin. |+| 4 | AVDD | power_in | Power-supply input, 2.7V to 5.5V. |+| 5 | VREFL | input | Negative reference input; VREFL must be below VREFH, with VREFL limited to AVDD/2 maximum per the reference input range. |+| 6 | GND | power_in | Ground reference point for all circuitry on the part. |+| 7 | VOUTC | output | Analog output voltage from DAC C. |+| 8 | VOUTD | output | Analog output voltage from DAC D. |+| 9 | SYNC | input | Level-triggered active-low frame sync for the input data; data are sampled on subsequent falling SCLK edges, the DAC output updates after the 24th clock, and a SYNC rising edge before the 24th clock aborts the write (Schmitt-trigger input). |+| 10 | SCLK | input | Serial clock input with data transfer rates up to 50MHz (Schmitt-trigger input). |+| 11 | DIN | input | Serial data input, clocked into the 24-bit input shift register on each falling SCLK edge (Schmitt-trigger input). |+| 12 | IOVDD | power_in | Digital input-output power supply, 1.8V to 5.5V per the electrical characteristics. |+| 13 | RST | input | Asynchronous active-low reset that sets all DAC channels to zero-scale (RSTSEL = 0) or mid-scale (RSTSEL = 1). |+| 14 | RSTSEL | input | Reset select: when low, input coding is binary; when high, input coding is two's complement. |+| 15 | ENABLE | input | Active-low enable that connects the SPI interface to the serial port. |+| 16 | LDAC | input | Load DACs input, rising-edge triggered, which loads all DAC registers. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Data Acquisition |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `DAC7565ICPWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `dac7565icpwr-etched.step` / `dac7565icpwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac7565icpwr.step` / `dac7565icpwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac7565) (51 pp, sha256 `676bd6014edb5cf1`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac7565icpwr-datasheet.pdf)
page.jsonadded+247@@ -0,0 +1,247 @@+{+ "slug": "dac7565icpwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "dac7565icpwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dac7565icpwr.kicad_sym",+ "dac7565icpwr.kicad_mod",+ "dac7565icpwr.glb",+ "dac7565icpwr.step",+ "dac7565icpwr.lbr",+ "docs/hero.png",+ "docs/dac7565icpwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "dac7565icpwr-hero.glb",+ "dac7565icpwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "DAC7565ICPWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Data Acquisition",+ "subcategory": "Digital To Analog Converters (DAC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dac7565",+ "parts": {+ "symbol": "dac7565icpwr.kicad_sym",+ "footprint": "dac7565icpwr.kicad_mod",+ "model_3d": "dac7565icpwr-hero.glb",+ "model_3d_plain": "dac7565icpwr.glb",+ "model_3d_step": "dac7565icpwr-etched.step",+ "model_3d_step_plain": "dac7565icpwr.step",+ "lbr": "dac7565icpwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C486033",+ "digikey": "296-DAC7565ICPWRTR-ND",+ "mouser": "595-DAC7565ICPWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T01:12:47Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-DAC7565ICPWRTR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-DAC7565ICPWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VOUTA",+ "type": "output",+ "description": "Analog output voltage from DAC A."+ },+ {+ "number": "2",+ "name": "VOUTB",+ "type": "output",+ "description": "Analog output voltage from DAC B."+ },+ {+ "number": "3",+ "name": "VREFH/VREFOUT",+ "type": "bidirectional",+ "description": "Positive reference input, or reference output at 2.5V when the internal reference is used; the internal reference can source up to 20mA at this pin."+ },+ {+ "number": "4",+ "name": "AVDD",+ "type": "power_in",+ "description": "Power-supply input, 2.7V to 5.5V."+ },+ {+ "number": "5",+ "name": "VREFL",+ "type": "input",+ "description": "Negative reference input; VREFL must be below VREFH, with VREFL limited to AVDD/2 maximum per the reference input range."+ },+ {+ "number": "6",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference point for all circuitry on the part."+ },+ {+ "number": "7",+ "name": "VOUTC",+ "type": "output",+ "description": "Analog output voltage from DAC C."+ },+ {+ "number": "8",+ "name": "VOUTD",+ "type": "output",+ "description": "Analog output voltage from DAC D."+ },+ {+ "number": "9",+ "name": "SYNC",+ "type": "input",+ "description": "Level-triggered active-low frame sync for the input data; data are sampled on subsequent falling SCLK edges, the DAC output updates after the 24th clock, and a SYNC rising edge before the 24th clock aborts the write (Schmitt-trigger input)."+ },+ {+ "number": "10",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input with data transfer rates up to 50MHz (Schmitt-trigger input)."+ },+ {+ "number": "11",+ "name": "DIN",+ "type": "input",+ "description": "Serial data input, clocked into the 24-bit input shift register on each falling SCLK edge (Schmitt-trigger input)."+ },+ {+ "number": "12",+ "name": "IOVDD",+ "type": "power_in",+ "description": "Digital input-output power supply, 1.8V to 5.5V per the electrical characteristics."+ },+ {+ "number": "13",+ "name": "RST",+ "type": "input",+ "description": "Asynchronous active-low reset that sets all DAC channels to zero-scale (RSTSEL = 0) or mid-scale (RSTSEL = 1)."+ },+ {+ "number": "14",+ "name": "RSTSEL",+ "type": "input",+ "description": "Reset select: when low, input coding is binary; when high, input coding is two's complement."+ },+ {+ "number": "15",+ "name": "ENABLE",+ "type": "input",+ "description": "Active-low enable that connects the SPI interface to the serial port."+ },+ {+ "number": "16",+ "name": "LDAC",+ "type": "input",+ "description": "Load DACs input, rising-edge triggered, which loads all DAC registers."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin 3 is a dual-function reference input/output; the pin table text is garbled in extraction, so the; The VREFL limit AVDD/2 comes from the reference input range row, which is conditioned on AVDD - (VRE"+ ],+ "pages_sent": 9,+ "cost_usd": 0.0633,+ "at": "2026-10-08T01:12:30"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dac7565",+ "pages": 51,+ "sha256": "676bd6014edb5cf1",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dac7565icpwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dac7565icpwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "839169c7e093bd3f25c4729ed3d122de88e5ccba12853308f131d03eec35e84c",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}