DAC7562TDGST

Texas Instruments · Digital To Analog Converters (DACs) · VSSOP-10-0.5mm

DAC7562TDGST from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VOUTA	output	Analog output voltage from DAC-A.
2	VOUTB	output	Analog output voltage from DAC-B.
3	GND	power_in	Ground reference point for all circuitry on the device.
4	LDAC	input	In synchronous mode it must be tied to GND permanently or held low before sending commands; in asynchronous mode a negative-edge trigger simultaneously updates the DAC output registers from the data buffers.
5	CLR	input	Falling-edge-sensitive asynchronous clear input that loads zero-scale (DAC7562T) into all input and DAC registers, and the device exits clear mode on the 24th falling edge of the next write.
6	SYNC	input	Active-low frame sync input (Schmitt-trigger); DAC output updates after the 24th SCLK falling edge, and a SYNC rising edge before the 23rd clock edge aborts the write sequence.
7	SCLK	input	Serial clock input (Schmitt-trigger) with data transfer rates up to 50 MHz.
8	DIN	input	Serial data input (Schmitt-trigger); data are clocked into the 24-bit input shift register on each falling SCLK edge.
9	AVDD	power_in	Power-supply input, 2.7 V to 5.5 V.
10	VREFIN/VREFOUT	bidirectional	Bidirectional voltage reference pin; provides a 2.5-V output when the internal reference is used, otherwise accepts an external reference input.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VSSOP-10-0.5mm
Category	ADC/DAC/Data Conversion
Pins	10

CAD (KiCad official)

Symbol: DAC7562TDGST
Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
3D model files: dac7562tdgst-etched.step / dac7562tdgst-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac7562tdgst.step / dac7562tdgst.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (63 pp, sha256 c924f9150c60d73e, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# DAC7562TDGST

**Texas Instruments** · Digital To Analog Converters (DACs) · VSSOP-10-0.5mm

DAC7562TDGST from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC-A. |
| 2 | VOUTB | output | Analog output voltage from DAC-B. |
| 3 | GND | power_in | Ground reference point for all circuitry on the device. |
| 4 | LDAC | input | In synchronous mode it must be tied to GND permanently or held low before sending commands; in asynchronous mode a negative-edge trigger simultaneously updates the DAC output registers from the data buffers. |
| 5 | CLR | input | Falling-edge-sensitive asynchronous clear input that loads zero-scale (DAC7562T) into all input and DAC registers, and the device exits clear mode on the 24th falling edge of the next write. |
| 6 | SYNC | input | Active-low frame sync input (Schmitt-trigger); DAC output updates after the 24th SCLK falling edge, and a SYNC rising edge before the 23rd clock edge aborts the write sequence. |
| 7 | SCLK | input | Serial clock input (Schmitt-trigger) with data transfer rates up to 50 MHz. |
| 8 | DIN | input | Serial data input (Schmitt-trigger); data are clocked into the 24-bit input shift register on each falling SCLK edge. |
| 9 | AVDD | power_in | Power-supply input, 2.7 V to 5.5 V. |
| 10 | VREFIN/VREFOUT | bidirectional | Bidirectional voltage reference pin; provides a 2.5-V output when the internal reference is used, otherwise accepts an external reference input. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |

## CAD (KiCad official)

- Symbol: `DAC7562TDGST`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files: `dac7562tdgst-etched.step` / `dac7562tdgst-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac7562tdgst.step` / `dac7562tdgst.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac8162t) (63 pp, sha256 `c924f9150c60d73e`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dac7562tdgst-datasheet.pdf)