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DAC7562TDGST
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Texas Instruments Digital To Analog Converters (DACs), VSSOP-10-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+47@@ -0,0 +1,47 @@+# DAC7562TDGST++**Texas Instruments** · Digital To Analog Converters (DACs) · VSSOP-10-0.5mm++DAC7562TDGST from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VOUTA | output | Analog output voltage from DAC-A. |+| 2 | VOUTB | output | Analog output voltage from DAC-B. |+| 3 | GND | power_in | Ground reference point for all circuitry on the device. |+| 4 | LDAC | input | In synchronous mode it must be tied to GND permanently or held low before sending commands; in asynchronous mode a negative-edge trigger simultaneously updates the DAC output registers from the data buffers. |+| 5 | CLR | input | Falling-edge-sensitive asynchronous clear input that loads zero-scale (DAC7562T) into all input and DAC registers, and the device exits clear mode on the 24th falling edge of the next write. |+| 6 | SYNC | input | Active-low frame sync input (Schmitt-trigger); DAC output updates after the 24th SCLK falling edge, and a SYNC rising edge before the 23rd clock edge aborts the write sequence. |+| 7 | SCLK | input | Serial clock input (Schmitt-trigger) with data transfer rates up to 50 MHz. |+| 8 | DIN | input | Serial data input (Schmitt-trigger); data are clocked into the 24-bit input shift register on each falling SCLK edge. |+| 9 | AVDD | power_in | Power-supply input, 2.7 V to 5.5 V. |+| 10 | VREFIN/VREFOUT | bidirectional | Bidirectional voltage reference pin; provides a 2.5-V output when the internal reference is used, otherwise accepts an external reference input. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VSSOP-10-0.5mm |+| Category | ADC/DAC/Data Conversion |+| Pins | 10 |++## CAD (KiCad official)++- Symbol: `DAC7562TDGST`+- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`+- 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)+- 3D model files: `dac7562tdgst-etched.step` / `dac7562tdgst-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac7562tdgst.step` / `dac7562tdgst.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac8162t) (63 pp, sha256 `c924f9150c60d73e`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac7562tdgst-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "adc-dac-data conversion",+ "dac7562tdgst",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dac7562tdgst.kicad_sym",+ "dac7562tdgst.kicad_mod",+ "dac7562tdgst.glb",+ "dac7562tdgst.step",+ "dac7562tdgst.lbr",+ "docs/hero.png",+ "docs/dac7562tdgst-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "dac7562tdgst-hero.glb",+ "dac7562tdgst-hero.overlay.json"+ ],+ "component": {+ "mpn": "DAC7562TDGST",+ "manufacturer": "Texas Instruments",+ "package": "VSSOP-10-0.5mm",+ "pin_count": 10,+ "category": "ADC/DAC/Data Conversion",+ "subcategory": "Digital To Analog Converters (DACs)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dac8162t",+ "parts": {+ "symbol": "dac7562tdgst.kicad_sym",+ "footprint": "dac7562tdgst.kicad_mod",+ "model_3d": "dac7562tdgst-hero.glb",+ "model_3d_plain": "dac7562tdgst.glb",+ "model_3d_step": "dac7562tdgst-etched.step",+ "model_3d_step_plain": "dac7562tdgst.step",+ "lbr": "dac7562tdgst.lbr"+ },+ "distributor_links": {+ "lcsc": "C1016154",+ "digikey": "296-DAC7562TDGSTTR-ND",+ "mouser": "595-DAC7562TDGST"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T19:55:17Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-DAC7562TDGSTTR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-DAC7562TDGST",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VOUTA",+ "type": "output",+ "description": "Analog output voltage from DAC-A."+ },+ {+ "number": "2",+ "name": "VOUTB",+ "type": "output",+ "description": "Analog output voltage from DAC-B."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference point for all circuitry on the device."+ },+ {+ "number": "4",+ "name": "LDAC",+ "type": "input",+ "description": "In synchronous mode it must be tied to GND permanently or held low before sending commands; in asynchronous mode a negative-edge trigger simultaneously updates the DAC output registers from the data buffers."+ },+ {+ "number": "5",+ "name": "CLR",+ "type": "input",+ "description": "Falling-edge-sensitive asynchronous clear input that loads zero-scale (DAC7562T) into all input and DAC registers, and the device exits clear mode on the 24th falling edge of the next write."+ },+ {+ "number": "6",+ "name": "SYNC",+ "type": "input",+ "description": "Active-low frame sync input (Schmitt-trigger); DAC output updates after the 24th SCLK falling edge, and a SYNC rising edge before the 23rd clock edge aborts the write sequence."+ },+ {+ "number": "7",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input (Schmitt-trigger) with data transfer rates up to 50 MHz."+ },+ {+ "number": "8",+ "name": "DIN",+ "type": "input",+ "description": "Serial data input (Schmitt-trigger); data are clocked into the 24-bit input shift register on each falling SCLK edge."+ },+ {+ "number": "9",+ "name": "AVDD",+ "type": "power_in",+ "description": "Power-supply input, 2.7 V to 5.5 V."+ },+ {+ "number": "10",+ "name": "VREFIN/VREFOUT",+ "type": "bidirectional",+ "description": "Bidirectional voltage reference pin; provides a 2.5-V output when the internal reference is used, otherwise accepts an external reference input."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The DGS (VSSOP-10) pinout was taken from the Pin Functions table on page 4, since the pin drawing te; Description for VREFIN/VREFOUT states the 2.5-V output only when the internal reference is used. The"+ ],+ "pages_sent": 13,+ "cost_usd": 0.0864,+ "at": "2026-10-08T19:54:58"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dac8162t",+ "pages": 63,+ "sha256": "c924f9150c60d73e",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 10,+ "described": 10,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dac7562tdgst.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4.9,+ 3,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b8f88eac3ce221c2ccb0b5048f9ad49c2ef4af148f8ae50c4e232e357683f547",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dac7562tdgst-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4.9,+ 3,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "5fa675c197a2be6f015e1b836428455e72e89093003ee66f09432e9a64702092",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}