component
CY8C4124LQI-443
Public Made by Adomby adom
Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
Ray
Publish 0.1.0
1c99acd
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393
{
"slug": "cy8c4124lqi-443",
"version": "0.1.0",
"type": "component",
"description": "Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"single chip microcomputer-microcontroller",
"cy8c4124lqi-443",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"cy8c4124lqi-443.kicad_sym",
"cy8c4124lqi-443.kicad_mod",
"cy8c4124lqi-443.glb",
"cy8c4124lqi-443.step",
"cy8c4124lqi-443.lbr",
"docs/hero.png",
"docs/cy8c4124lqi-443-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"cy8c4124lqi-443-hero.glb",
"cy8c4124lqi-443-hero.overlay.json",
"cy8c4124lqi-443-etched.glb"
],
"component": {
"mpn": "CY8C4124LQI-443",
"manufacturer": "Cypress Semicon",
"package": "QFN-40(6x6)",
"pin_count": 41,
"category": "Single Chip Microcomputer/Microcontroller",
"subcategory": "Microcontroller Units (MCUs/MPUs/SOCs)",
"datasheet": "https://www.infineon.com/dgdl/Infineon-PSoC_4_PSoC_4100_Family-DataSheet-v12_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ec86cc240d7&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files",
"parts": {
"symbol": "cy8c4124lqi-443.kicad_sym",
"footprint": "cy8c4124lqi-443.kicad_mod",
"model_3d": "cy8c4124lqi-443-hero.glb",
"model_3d_plain": "cy8c4124lqi-443-etched.glb",
"model_3d_step": "cy8c4124lqi-443-etched.step",
"model_3d_step_plain": "cy8c4124lqi-443.step",
"lbr": "cy8c4124lqi-443.lbr"
},
"distributor_links": {
"lcsc": "C2959309",
"digikey": "CY8C4124LQI-443-ND",
"mouser": "727-CY8C4124LQI-443"
},
"distributor_check": {
"checked_at": "2026-10-31T01:12:43Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "CY8C4124LQI-443-ND",
"status": "found"
},
"mouser": {
"pn": "727-CY8C4124LQI-443",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "P2.0",
"type": "bidirectional",
"description": "Port 2 Pin 0 GPIO with LCD, CSD CapSense and SAR mux input sarmux.0; Port 2 carries the high-speed analog inputs for the SAR mux."
},
{
"number": "2",
"name": "P2.1",
"type": "bidirectional",
"description": "Port 2 Pin 1 GPIO with LCD, CSD CapSense and SAR mux input sarmux.1."
},
{
"number": "3",
"name": "P2.2",
"type": "bidirectional",
"description": "Port 2 Pin 2 GPIO with LCD, CSD CapSense and SAR mux input sarmux.2."
},
{
"number": "4",
"name": "P2.3",
"type": "bidirectional",
"description": "Port 2 Pin 3 GPIO with LCD, CSD CapSense and SAR mux input sarmux.3."
},
{
"number": "5",
"name": "P2.4",
"type": "bidirectional",
"description": "Port 2 Pin 4 GPIO with LCD, CSD CapSense, SAR mux input sarmux.4 and TCPWM0 output tcpwm0_p[1]."
},
{
"number": "6",
"name": "P2.5",
"type": "bidirectional",
"description": "Port 2 Pin 5 GPIO with LCD, CSD CapSense, SAR mux input sarmux.5 and TCPWM0 complementary output tcpwm0_n[1]."
},
{
"number": "7",
"name": "P2.6",
"type": "bidirectional",
"description": "Port 2 Pin 6 GPIO with LCD, CSD CapSense, SAR mux input sarmux.6 and TCPWM1 output tcpwm1_p[1]."
},
{
"number": "8",
"name": "P2.7",
"type": "bidirectional",
"description": "Port 2 Pin 7 GPIO with LCD, CSD CapSense, SAR mux input sarmux.7 and TCPWM1 complementary output tcpwm1_n[1]."
},
{
"number": "9",
"name": "VSS",
"type": "power_in",
"description": "Ground pin."
},
{
"number": "10",
"name": "P3.0",
"type": "bidirectional",
"description": "Port 3 Pin 0 GPIO with LCD, CSD, PWM tcpwm0_p[0] and SCB1 UART RX / I2C SCL / SPI MOSI alternates."
},
{
"number": "11",
"name": "P3.1",
"type": "bidirectional",
"description": "Port 3 Pin 1 GPIO with LCD, CSD, PWM tcpwm0_n[0] and SCB1 UART TX / I2C SDA / SPI MISO alternates."
},
{
"number": "12",
"name": "P3.2",
"type": "bidirectional",
"description": "Port 3 Pin 2 GPIO with LCD, CSD, PWM tcpwm1_p[0], SCB1 SPI clock and SWD I/O (swd_io[0]); this pin is an SWD pin after boot (reset)."
},
{
"number": "13",
"name": "P3.3",
"type": "bidirectional",
"description": "Port 3 Pin 3 GPIO with LCD, CSD, PWM tcpwm1_n[0], SCB1 SPI slave select 0 and SWD clock (swd_clk[0]); this pin is an SWD pin after boot (reset)."
},
{
"number": "14",
"name": "P3.4",
"type": "bidirectional",
"description": "Port 3 Pin 4 GPIO with LCD, CSD, PWM tcpwm2_p[0] and SCB1 SPI slave select 1."
},
{
"number": "15",
"name": "P3.5",
"type": "bidirectional",
"description": "Port 3 Pin 5 GPIO with LCD, CSD, PWM tcpwm2_n[0] and SCB1 SPI slave select 2."
},
{
"number": "16",
"name": "P3.6",
"type": "bidirectional",
"description": "Port 3 Pin 6 GPIO with LCD, CSD, PWM tcpwm3_p[0] and SCB1 SPI slave select 3."
},
{
"number": "17",
"name": "P3.7",
"type": "bidirectional",
"description": "Port 3 Pin 7 GPIO with LCD, CSD and PWM tcpwm3_n[0] alternates."
},
{
"number": "18",
"name": "P4.0",
"type": "bidirectional",
"description": "Port 4 Pin 0 GPIO with LCD, CSD and SCB0 UART RX / I2C SCL / SPI MOSI alternates."
},
{
"number": "19",
"name": "P4.1",
"type": "bidirectional",
"description": "Port 4 Pin 1 GPIO with LCD, CSD and SCB0 UART TX / I2C SDA / SPI MISO alternates."
},
{
"number": "20",
"name": "P4.2",
"type": "bidirectional",
"description": "Port 4 Pin 2 GPIO with LCD, CSD, CSD modulator connection csd_c_mod and SCB0 SPI clock."
},
{
"number": "21",
"name": "P4.3",
"type": "bidirectional",
"description": "Port 4 Pin 3 GPIO with LCD, CSD, CSD shield tank connection csd_c_sh_tank and SCB0 SPI slave select 0."
},
{
"number": "22",
"name": "P0.0",
"type": "bidirectional",
"description": "Port 0 Pin 0 GPIO with LCD, CSD, comparator 1 positive input comp1_inp and SCB0 SPI slave select 1."
},
{
"number": "23",
"name": "P0.1",
"type": "bidirectional",
"description": "Port 0 Pin 1 GPIO with LCD, CSD, comparator 1 negative input comp1_inn and SCB0 SPI slave select 2."
},
{
"number": "24",
"name": "P0.2",
"type": "bidirectional",
"description": "Port 0 Pin 2 GPIO with LCD, CSD, comparator 2 positive input comp2_inp and SCB0 SPI slave select 3."
},
{
"number": "25",
"name": "P0.3",
"type": "bidirectional",
"description": "Port 0 Pin 3 GPIO with LCD, CSD and comparator 2 negative input comp2_inn."
},
{
"number": "26",
"name": "P0.4",
"type": "bidirectional",
"description": "Port 0 Pin 4 GPIO with LCD, CSD and SCB1 UART RX[1] / I2C SCL[1] / SPI MOSI[1] alternates."
},
{
"number": "27",
"name": "P0.5",
"type": "bidirectional",
"description": "Port 0 Pin 5 GPIO with LCD, CSD and SCB1 UART TX[1] / I2C SDA[1] / SPI MISO[1] alternates."
},
{
"number": "28",
"name": "P0.6",
"type": "bidirectional",
"description": "Port 0 Pin 6 GPIO with LCD, CSD, external clock input ext_clk and SCB1 SPI clock[1]."
},
{
"number": "29",
"name": "P0.7",
"type": "bidirectional",
"description": "Port 0 Pin 7 GPIO with LCD, CSD, wakeup input and SCB1 SPI slave select 0[1]."
},
{
"number": "30",
"name": "XRES",
"type": "input",
"description": "Chip reset input, active low; it has an internal pull-up resistor that is always enabled."
},
{
"number": "31",
"name": "VCCD",
"type": "power_out",
"description": "Regulated digital supply: connect to a 1 µF capacitor (datasheet range 1 µF to 1.6 µF, X5R or better) in unregulated mode, or drive at 1.8 V ±5% in regulated mode."
},
{
"number": "32",
"name": "VDDD",
"type": "power_in",
"description": "Digital supply, 1.8 V to 5.5 V, powering the digital section (and the analog section where no VDDA pin exists)."
},
{
"number": "33",
"name": "VDDA",
"type": "power_in",
"description": "Analog supply, 1.8 V to 5.5 V, equal to VDDD and must be shorted to VDDD in unregulated mode."
},
{
"number": "34",
"name": "VSSA",
"type": "power_in",
"description": "Analog ground pin, shorted to VSS in unregulated mode."
},
{
"number": "35",
"name": "P1.0",
"type": "bidirectional",
"description": "Port 1 Pin 0 GPIO with LCD, CSD, CTB op-amp 0 non-inverting input ctb.oa0.inp and PWM tcpwm2_p[1]."
},
{
"number": "36",
"name": "P1.1",
"type": "bidirectional",
"description": "Port 1 Pin 1 GPIO with LCD, CSD, CTB op-amp 0 inverting input ctb.oa0.inm and PWM tcpwm2_n[1]."
},
{
"number": "37",
"name": "P1.2",
"type": "bidirectional",
"description": "Port 1 Pin 2 GPIO with LCD, CSD, CTB op-amp 0 output ctb.oa0.out and PWM tcpwm3_p[1]."
},
{
"number": "38",
"name": "P1.3",
"type": "bidirectional",
"description": "Port 1 Pin 3 GPIO with LCD, CSD, CTB op-amp 1 output ctb.oa1.out and PWM tcpwm3_n[1]."
},
{
"number": "39",
"name": "P1.4",
"type": "bidirectional",
"description": "Port 1 Pin 4 GPIO with LCD, CSD and CTB op-amp 1 inverting input ctb.oa1.inm."
},
{
"number": "40",
"name": "P1.7/VREF",
"type": "bidirectional",
"description": "Port 1 Pin 7 GPIO with LCD, CSD, CTB op-amp 1 alternate non-inverting input ctb.oa1.inp_alt and optional external reference input/bypass for the SAR (ext_vref)."
},
{
"number": "41",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Package mapping: the ordering table row for CY8C4124LQI-443 shows 34 GPIOs. The 40-QFN column matche; Package dimension: the hint 'QFN-40(6x6)' could not be confirmed. The text says only '40-pin QFN' / ; Pins 9 and 34 are listed as VSS and VSSA respectively in the 40-QFN column. The exposed center pad (",
"exposed pad 41 added from the footprint"
],
"pages_sent": 24,
"cost_usd": 0.1726,
"at": "2026-10-31T01:12:02"
},
"datasheet": {
"url": "https://www.infineon.com/dgdl/Infineon-PSoC_4_PSoC_4100_Family-DataSheet-v12_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ec86cc240d7&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files",
"pages": 44,
"sha256": "96f5358c3c46932a",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 41,
"described": 41,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "cy8c4124lqi-443.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.0,
6.0,
1.0
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "e5b4286c2329085d9ef7f90d5eb5bf41a435241ecc1baaf1383823b6d6a946ae",
"checked": "2026-10-31",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "cy8c4124lqi-443-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.0,
6.0,
1.0
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "856550212293a83ebf80f4f41e366ae918455832c2cf731ea3414af3448e7a01",
"checked": "2026-10-31",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}