component

CY8C4124LQI-443

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercy8c4124lqi-443factory-2.0.0extractor-text

Verified CY8C4124LQI-443

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY8C4124LQI-443 · QFN-40(6x6) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 44-page datasheet
  • ✓distributor: lcsc C2959309, digikey CY8C4124LQI-443-ND, mouser 727-CY8C4124LQI-443
  • ✓family: QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-espmlpsd/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy8c4124lqi-443.kicad_sym✓ cy8c4124lqi-443.kicad_mod✓ cy8c4124lqi-443.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cy8c4124lqi-443: viewers · Ray
cy8c4124lqi-443-etched.glb Publish 0.1.0 · Ray
cy8c4124lqi-443-etched.step cy8c4124lqi-443: factory component page (tier=mfr) · Ray
cy8c4124lqi-443-hero.glb cy8c4124lqi-443: hero GLB from the etched model (keeps the MPN mark) · Ray
cy8c4124lqi-443-hero.overlay.json Publish 0.1.0 · Ray
cy8c4124lqi-443.glb Publish 0.1.0 · Ray
cy8c4124lqi-443.kicad_mod Publish 0.1.0 · Ray
cy8c4124lqi-443.kicad_sym Publish 0.1.0 · Ray
cy8c4124lqi-443.lbr Publish 0.1.0 · Ray
cy8c4124lqi-443.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 41 pins · Ray

CY8C4124LQI-443

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-40(6x6)

CY8C4124LQI-443 from Cypress Semicon, in a QFN-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2.0 bidirectional Port 2 Pin 0 GPIO with LCD, CSD CapSense and SAR mux input sarmux.0; Port 2 carries the high-speed analog inputs for the SAR mux.
2 P2.1 bidirectional Port 2 Pin 1 GPIO with LCD, CSD CapSense and SAR mux input sarmux.1.
3 P2.2 bidirectional Port 2 Pin 2 GPIO with LCD, CSD CapSense and SAR mux input sarmux.2.
4 P2.3 bidirectional Port 2 Pin 3 GPIO with LCD, CSD CapSense and SAR mux input sarmux.3.
5 P2.4 bidirectional Port 2 Pin 4 GPIO with LCD, CSD CapSense, SAR mux input sarmux.4 and TCPWM0 output tcpwm0_p[1].
6 P2.5 bidirectional Port 2 Pin 5 GPIO with LCD, CSD CapSense, SAR mux input sarmux.5 and TCPWM0 complementary output tcpwm0_n[1].
7 P2.6 bidirectional Port 2 Pin 6 GPIO with LCD, CSD CapSense, SAR mux input sarmux.6 and TCPWM1 output tcpwm1_p[1].
8 P2.7 bidirectional Port 2 Pin 7 GPIO with LCD, CSD CapSense, SAR mux input sarmux.7 and TCPWM1 complementary output tcpwm1_n[1].
9 VSS power_in Ground pin.
10 P3.0 bidirectional Port 3 Pin 0 GPIO with LCD, CSD, PWM tcpwm0_p[0] and SCB1 UART RX / I2C SCL / SPI MOSI alternates.
11 P3.1 bidirectional Port 3 Pin 1 GPIO with LCD, CSD, PWM tcpwm0_n[0] and SCB1 UART TX / I2C SDA / SPI MISO alternates.
12 P3.2 bidirectional Port 3 Pin 2 GPIO with LCD, CSD, PWM tcpwm1_p[0], SCB1 SPI clock and SWD I/O (swd_io[0]); this pin is an SWD pin after boot (reset).
13 P3.3 bidirectional Port 3 Pin 3 GPIO with LCD, CSD, PWM tcpwm1_n[0], SCB1 SPI slave select 0 and SWD clock (swd_clk[0]); this pin is an SWD pin after boot (reset).
14 P3.4 bidirectional Port 3 Pin 4 GPIO with LCD, CSD, PWM tcpwm2_p[0] and SCB1 SPI slave select 1.
15 P3.5 bidirectional Port 3 Pin 5 GPIO with LCD, CSD, PWM tcpwm2_n[0] and SCB1 SPI slave select 2.
16 P3.6 bidirectional Port 3 Pin 6 GPIO with LCD, CSD, PWM tcpwm3_p[0] and SCB1 SPI slave select 3.
17 P3.7 bidirectional Port 3 Pin 7 GPIO with LCD, CSD and PWM tcpwm3_n[0] alternates.
18 P4.0 bidirectional Port 4 Pin 0 GPIO with LCD, CSD and SCB0 UART RX / I2C SCL / SPI MOSI alternates.
19 P4.1 bidirectional Port 4 Pin 1 GPIO with LCD, CSD and SCB0 UART TX / I2C SDA / SPI MISO alternates.
20 P4.2 bidirectional Port 4 Pin 2 GPIO with LCD, CSD, CSD modulator connection csd_c_mod and SCB0 SPI clock.
21 P4.3 bidirectional Port 4 Pin 3 GPIO with LCD, CSD, CSD shield tank connection csd_c_sh_tank and SCB0 SPI slave select 0.
22 P0.0 bidirectional Port 0 Pin 0 GPIO with LCD, CSD, comparator 1 positive input comp1_inp and SCB0 SPI slave select 1.
23 P0.1 bidirectional Port 0 Pin 1 GPIO with LCD, CSD, comparator 1 negative input comp1_inn and SCB0 SPI slave select 2.
24 P0.2 bidirectional Port 0 Pin 2 GPIO with LCD, CSD, comparator 2 positive input comp2_inp and SCB0 SPI slave select 3.
25 P0.3 bidirectional Port 0 Pin 3 GPIO with LCD, CSD and comparator 2 negative input comp2_inn.
26 P0.4 bidirectional Port 0 Pin 4 GPIO with LCD, CSD and SCB1 UART RX[1] / I2C SCL[1] / SPI MOSI[1] alternates.
27 P0.5 bidirectional Port 0 Pin 5 GPIO with LCD, CSD and SCB1 UART TX[1] / I2C SDA[1] / SPI MISO[1] alternates.
28 P0.6 bidirectional Port 0 Pin 6 GPIO with LCD, CSD, external clock input ext_clk and SCB1 SPI clock[1].
29 P0.7 bidirectional Port 0 Pin 7 GPIO with LCD, CSD, wakeup input and SCB1 SPI slave select 0[1].
30 XRES input Chip reset input, active low; it has an internal pull-up resistor that is always enabled.
31 VCCD power_out Regulated digital supply: connect to a 1 µF capacitor (datasheet range 1 µF to 1.6 µF, X5R or better) in unregulated mode, or drive at 1.8 V ±5% in regulated mode.
32 VDDD power_in Digital supply, 1.8 V to 5.5 V, powering the digital section (and the analog section where no VDDA pin exists).
33 VDDA power_in Analog supply, 1.8 V to 5.5 V, equal to VDDD and must be shorted to VDDD in unregulated mode.
34 VSSA power_in Analog ground pin, shorted to VSS in unregulated mode.
35 P1.0 bidirectional Port 1 Pin 0 GPIO with LCD, CSD, CTB op-amp 0 non-inverting input ctb.oa0.inp and PWM tcpwm2_p[1].
36 P1.1 bidirectional Port 1 Pin 1 GPIO with LCD, CSD, CTB op-amp 0 inverting input ctb.oa0.inm and PWM tcpwm2_n[1].
37 P1.2 bidirectional Port 1 Pin 2 GPIO with LCD, CSD, CTB op-amp 0 output ctb.oa0.out and PWM tcpwm3_p[1].
38 P1.3 bidirectional Port 1 Pin 3 GPIO with LCD, CSD, CTB op-amp 1 output ctb.oa1.out and PWM tcpwm3_n[1].
39 P1.4 bidirectional Port 1 Pin 4 GPIO with LCD, CSD and CTB op-amp 1 inverting input ctb.oa1.inm.
40 P1.7/VREF bidirectional Port 1 Pin 7 GPIO with LCD, CSD, CTB op-amp 1 alternate non-inverting input ctb.oa1.inp_alt and optional external reference input/bypass for the SAR (ext_vref).
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package QFN-40(6x6)
Category Single Chip Microcomputer/Microcontroller
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Absolute max digital supply relative to VSSD VDDD_ABS -0.5 6 V Absolute max 19
Direct digital core voltage input relative to VSSD VCCD_ABS -0.5 1.95 V Absolute max 19
GPIO voltage VGPIO_ABS -0.5 V Absolute max 19
Maximum current per GPIO IGPIO_ABS -25 25 mA Absolute max 19
GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS IGPIO_injection -0.5 0.5 mA Absolute max, current injected per pin 19
Electrostatic discharge human body model ESD_HBM 2200 V 19
Electrostatic discharge charged device model ESD_CDM 500 V 19
Pin current for latch-up LU -200 200 mA 19
Maximum storage temperature 150 °C Per JESD22-A103 (Table 1 Note 1) 19
Power Supply Input Voltage (VDDA = VDDD = VDD) VDD 1.8 5.5 V With regulator enabled 19
Power Supply Input Voltage unregulated VDDD 1.71 1.8 1.89 V Internally unregulated Supply 19
External Regulator voltage (VCCD) bypass CEFC 1 1.3 1.6 µF X5R ceramic or better 19
Power supply decoupling capacitor CEXC 1 µF X5R ceramic or better 19
Execute from Flash; CPU at 6 MHz IDD4 2.8 mA Active Mode, VDD = 1.71 V to 5.5 V; Execute from Flash; CPU at 6 MHz 19
Execute from Flash; CPU at 12 MHz IDD7 4.2 mA Active Mode, VDD = 1.71 V to 5.5 V; Execute from Flash; CPU at 12 MHz 19
Execute from Flash; CPU at 24 MHz IDD12 7.2 mA Active Mode, VDD = 1.71 V to 5.5 V; Execute from Flash; CPU at 24 MHz 19
Sleep mode current, I2C wakeup, WDT, and Comparators on, 6 MHz IDD20 1.3 1.8 mA Sleep Mode, VDD = 1.7 V to 5.5 V; VDD = 1.71 to 5.5 V 19
Sleep mode current, I2C wakeup, WDT, and Comparators on, 12 MHz IDD20A 1.7 2.2 mA Sleep Mode, VDD = 1.7 V to 5.5 V; VDD = 1.71 to 5.5 V 19
Deep Sleep current, I2C wakeup and WDT on IDD27 45 µA Deep Sleep, VDD = 1.8 V to 3.6 V (Regulator on); T = 85 °C 20
Deep Sleep current, I2C wakeup and WDT on IDD29 1.5 15 µA Deep Sleep, VDD = 3.6 V to 5.5 V; Typ at 25 °C, Max at 85 °C 20
Deep Sleep current, I2C wakeup and WDT on IDD33 60 µA Deep Sleep, VDD = 1.71 V to 1.89 V (Regulator bypassed); T = 85 °C 20
Hibernate current, GPIO and Reset active IDD36 1000 nA Hibernate, VDD = 1.8 V to 3.6 V (Regulator on); T = 85 °C 20
Stop Mode current IDD43A 20 80 nA Stop Mode current; VDD = 3.3 V; Typ at 25 °C, Max at 85 °C 20
Supply current while XRES asserted IDD_XR 2 5 mA 20
CPU frequency FCPU 24 MHz 1.71 VDD 5.5 19
Wakeup from Deep Sleep mode TDEEPSLEEP 25 µs 24-MHz IMO. Guaranteed by characterization 19
Wakeup from Hibernate and Stop modes THIBERNATE 2 ms Guaranteed by characterization 19
External reset pulse width TRESETWIDTH 1 µs Guaranteed by characterization 19
Number of wait states at 24 MHz TWS24 0 CPU execution from Flash. Guaranteed by characterization 33
Trimmed internal reference to SAR VREFSAR -1 1 % Percentage of Vbg (1.024 V). Guaranteed by characterization 33
Clock switching from clk1 to clk2 in clk1 periods TCLKSWITCH 3 4 Periods Guaranteed by design 33
Operating ambient temperature TA -40 25 105 °C 36
Operating junction temperature TJ -40 125 °C 36
Package thermal resistance junction-to-ambient, 40-pin QFN TJA 15.34 °C/Watt 36
Package thermal resistance junction-to-case, 40-pin QFN TJC 2.5 °C/Watt 36

CAD (KiCad official)

  • Symbol: CY8C4124LQI-443
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: QFN-40(6x6) (KiCad packages3D, STEP)
  • 3D model files: cy8c4124lqi-443-etched.step / cy8c4124lqi-443-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4124lqi-443.step / cy8c4124lqi-443.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (44 pp, sha256 96f5358c3c46932a, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF