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CY8C4045LQI-S411

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY8C4045LQI-S411

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-24(4x4)

CY8C4045LQI-S411 from Cypress Semicon, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.7 bidirectional GPIO port 1 bit 7 with no alternate function listed in the pin assignment table.
2 P2.0 bidirectional GPIO that can be Smart I/O prgio[0].io[0], tcpwm.line[4]:0, csd.comp, tcpwm.tr_in[4], or Deep Sleep scb[1] I2C SCL:1 / SPI MOSI:2.
3 P2.1 bidirectional GPIO that can be Smart I/O prgio[0].io[1], tcpwm.line_compl[4]:0, tcpwm.tr_in[5], or Deep Sleep scb[1] I2C SDA:1 / SPI MISO:2.
4 P2.6 bidirectional GPIO that can be Smart I/O prgio[0].io[6], tcpwm.line[1]:1, or scb[1] spi_select3:1.
5 P2.7 bidirectional GPIO that can be Smart I/O prgio[0].io[7], tcpwm.line_compl[1]:1, or Deep Sleep lpcomp.comp[0]:1.
6 P3.0 bidirectional GPIO that can be Smart I/O prgio[1].io[0], tcpwm.line[0]:0, scb[1] UART RX:1, or Deep Sleep scb[1] I2C SCL:2 / SPI MOSI:0.
7 P3.2 bidirectional GPIO that can be Smart I/O prgio[1].io[2], tcpwm.line[1]:0, scb[1] UART CTS:1, SWD data (cpuss.swd_data), or scb[1] SPI clock:0.
8 P3.3 bidirectional GPIO that can be Smart I/O prgio[1].io[3], tcpwm.line_compl[1]:0, scb[1] UART RTS:1, SWD clock (cpuss.swd_clk), or scb[1] spi_select0:0.
9 P4.0 bidirectional GPIO that can be CAPSENSE external reference csd.vref_ext, scb[0] UART RX:0, tcpwm.tr_in[10], or Deep Sleep scb[0] I2C SCL:1 / SPI MOSI:0.
10 P4.1 bidirectional GPIO that can be CAPSENSE csd.cshieldpads, scb[0] UART TX:0, tcpwm.tr_in[11], or Deep Sleep scb[0] I2C SDA:1 / SPI MISO:0.
11 P4.2 bidirectional GPIO that can be CAPSENSE modulator capacitor pad csd.cmodpad, scb[0] UART CTS:0, lpcomp.comp[0]:0, or scb[0] SPI clock:0.
12 P4.3 bidirectional GPIO that can be CAPSENSE csd.csh_tank, scb[0] UART RTS:0, lpcomp.comp[1]:0, or scb[0] spi_select0:0.
13 P0.0 bidirectional GPIO that can be low-power comparator input lpcomp.in_p[0], tcpwm.tr_in[0], or scb[0] spi_select1:0.
14 P0.1 bidirectional GPIO that can be low-power comparator input lpcomp.in_n[0], tcpwm.tr_in[1], or scb[0] spi_select2:0.
15 P0.4 bidirectional GPIO that can be watch crystal input wco.wco_in, scb[1] UART RX:0, or Deep Sleep scb[1] I2C SCL:0 / SPI MOSI:1.
16 P0.5 bidirectional GPIO that can be watch crystal output wco.wco_out, scb[1] UART TX:0, or Deep Sleep scb[1] I2C SDA:0 / SPI MISO:1.
17 P0.6 bidirectional GPIO that can be external clock input srss.ext_clk, scb[1] UART CTS:0, or scb[1] SPI clock:1.
18 XRES input External reset input pin.
19 VCCD power_out Regulated digital supply (1.8 V ± 5%); must be bypassed to ground with a 0.1 µF X5R ceramic or better capacitor and not connected to anything else in the 1.8 V to 5.5 V supply mode.
20 VSSD power_in Ground pin for the digital section.
21 VDD power_in Power supply to all sections of the chip, 1.8 V to 5.5 V (or 1.71 V to 1.89 V when externally regulated with VCCD shorted).
22 VSSA power_in Ground pin for the analog section.
23 P1.2 bidirectional GPIO that can be tcpwm.line[3]:1, scb[0] UART CTS:1, tcpwm.tr_in[2], or scb[0] SPI clock:1.
24 P1.3 bidirectional GPIO that can be tcpwm.line_compl[3]:1, scb[0] UART RTS:1, tcpwm.tr_in[3], or scb[0] spi_select0:1.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package QFN-24(4x4)
Category Single Chip Microcomputer/Microcontroller
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDDD_ABS -0.5 6 V 21
Direct digital core voltage input relative to VSS VCCD_ABS -0.5 1.95 V 21
GPIO voltage VGPIO_ABS -0.5 V Max is VDD + 0.5 21
Maximum current per GPIO IGPIO_ABS -25 25 mA 21
GPIO injection current IGPIO_injection -0.5 0.5 mA Max for VIH > VDDD, Min for VIL < VSS; current injected per pin 21
ESD human body model ESD_HBM 2200 V 21
ESD charged device model ESD_CDM 500 V 21
Pin current for latch-up LU -140 140 mA 21
Power supply input voltage (internally regulated) VDD 1.8 5.5 V Internally regulated supply 22
Power supply input voltage (VCCD = VDD = VDDA) VDD 1.71 1.89 V Internally unregulated supply 22
Output voltage (for core logic) VCCD 1.8 V 22
External regulator voltage bypass CEFC 0.1 µF X5R ceramic or better 22
Power supply bypass capacitor CEXC 1 µF X5R ceramic or better 22
Active mode current, execute from flash, CPU at 6 MHz IDD5 1.2 2 mA Active mode, VDD = 1.8 V to 5.5 V 22
Active mode current, execute from flash, CPU at 24 MHz IDD8 2.4 4 mA Active mode, VDD = 1.8 V to 5.5 V 22
Active mode current, execute from flash, CPU at 48 MHz IDD11 4.6 5.9 mA Active mode, VDD = 1.8 V to 5.5 V 22
Sleep current, I2C wakeup, WDT, comparators on IDD17 1.1 1.6 mA VDDD = 1.8 V to 5.5 V (Regulator on); 6 MHz 22
Sleep current, I2C wakeup, WDT, comparators on IDD20 1.4 1.9 mA VDDD = 1.8 V to 5.5 V (Regulator on); 12 MHz 22
Sleep current, I2C wakeup, WDT, comparators on IDD23 0.7 0.9 mA VDDD = 1.71 V to 1.89 V (Regulator bypassed); 6 MHz 22
Sleep current, I2C wakeup, WDT, comparators on IDD23A 0.9 1.1 mA VDDD = 1.71 V to 1.89 V (Regulator bypassed); 12 MHz 22
Deep Sleep current, I2C wakeup and WDT on IDD26 2.5 60 µA VDD = 1.8 V to 3.6 V (Regulator on) 22
Supply current while XRES asserted IDD_XR 2 5 mA 22
IMO operating current at 48 MHz IIMO1 250 µA 39
IMO operating current at 24 MHz IIMO2 180 µA 39
IMO frequency variation at 24, 32, and 48 MHz (trimmed) FIMOTOL1 -2 2 % At -40°C to 85°C, for industrial temperature range and original extended industrial range parts 39
IMO startup time TSTARTIMO 7 µs 39
RMS jitter at 24 MHz TJITRMSIMO2 145 ps 39
ILO operating current IILO1 0.3 1.05 µA 40
ILO startup time TSTARTILO1 2 ms 40
ILO duty cycle TILODUTY 40 50 60 % 40
ILO frequency range FILOTRIM1 20 40 80 kHz 40
WCO crystal frequency FWCO 32.768 kHz 40
WCO frequency tolerance FTOL 50 250 ppm With 20-ppm crystal 40
WCO equivalent series resistance ESR 50 kΩ 40
WCO drive level PD 1 µW 40
WCO startup time TSTART 500 ms 40
WCO crystal load capacitance CL 6 12.5 pF 40
WCO crystal shunt capacitance C0 1.35 pF 40
WCO operating current (high power mode) IWCO1 8 µA 40
WCO operating current (low power mode) IWCO2 1 µA 40
External clock input frequency ExtClkFreq 0 48 MHz 41
External clock duty cycle ExtClkDuty 45 55 % Measured at VDD/2 41
System clock source switching time TCLKSWITCH 3 4 Periods 41
Max delay added by Smart I/O in Bypass Mode PRG_BYPASS 1.6 ns 41
Operating ambient temperature TA -40 25 105 °C 44
Operating junction temperature TJ -40 125 °C 44
Package thermal resistance junction-to-ambient TJA 21.7 °C/W 24L QFN 44
Package thermal resistance junction-to-case TJC 5.6 °C/W 24L QFN 44

CAD (KiCad official)

  • Symbol: CY8C4045LQI-S411
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: cy8c4045lqi-s411-etched.step / cy8c4045lqi-s411-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4045lqi-s411.step / cy8c4045lqi-s411.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (58 pp, sha256 493ab905a29a5d98, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF