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CY8C4025LQI-S401T

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY8C4025LQI-S401T

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-24-EP(4x4)

CY8C4025LQI-S401T from Cypress Semicon, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.7 bidirectional General-purpose I/O port 1 bit 7 with programmable drive modes; can be CAPSENSE, analog or digital, with no alternate peripheral function listed.
2 P2.0 bidirectional GPIO port 2 bit 0 with Smart I/O prgio[0].io[0], TCPWM line[4], csd.comp and SCB1 I2C SCL/SPI MOSI Deep Sleep alternate functions.
3 P2.1 bidirectional GPIO port 2 bit 1 with Smart I/O prgio[0].io[1], TCPWM line_compl[4] and SCB1 I2C SDA/SPI MISO Deep Sleep alternate functions.
4 P2.6 bidirectional GPIO port 2 bit 6 with Smart I/O prgio[0].io[6], TCPWM line[1] and SCB1 SPI select3 alternate functions.
5 P2.7 bidirectional GPIO port 2 bit 7 with Smart I/O prgio[0].io[7], TCPWM line_compl[1] and low-power comparator output lpcomp.comp[0] Deep Sleep function.
6 P3.0 bidirectional GPIO port 3 bit 0 with Smart I/O prgio[1].io[0], TCPWM line[0], SCB1 UART RX, I2C SCL and SPI MOSI alternate functions.
7 P3.2 bidirectional GPIO port 3 bit 2 with Smart I/O prgio[1].io[2], TCPWM line[1], SCB1 UART CTS/SPI clock and SWD data (cpuss.swd_data) function.
8 P3.3 bidirectional GPIO port 3 bit 3 with Smart I/O prgio[1].io[3], TCPWM line_compl[1], SCB1 UART RTS/SPI select0 and SWD clock (cpuss.swd_clk) function.
9 P4.0 bidirectional GPIO port 4 bit 0 with analog function csd.vref_ext (external CSD reference) and SCB0 UART RX, I2C SCL and SPI MOSI alternate functions.
10 P4.1 bidirectional GPIO port 4 bit 1 with analog function csd.cshieldpads and SCB0 UART TX, I2C SDA and SPI MISO alternate functions.
11 P4.2 bidirectional GPIO port 4 bit 2 with analog function csd.cmodpad (CSD modulator capacitor) and lpcomp.comp[0] and SCB0 SPI clock alternate functions.
12 P4.3 bidirectional GPIO port 4 bit 3 with analog function csd.csh_tank and lpcomp.comp[1] and SCB0 UART RTS/SPI select0 alternate functions.
13 P0.0 bidirectional GPIO port 0 bit 0 with analog low-power comparator input lpcomp.in_p[0], TCPWM trigger input tr_in[0] and SCB0 SPI select1 function.
14 P0.1 bidirectional GPIO port 0 bit 1 with analog low-power comparator input lpcomp.in_n[0], TCPWM trigger input tr_in[1] and SCB0 SPI select2 function.
15 P0.4 bidirectional GPIO port 0 bit 4 with watch crystal oscillator input (wco.wco_in), SCB1 UART RX and I2C SCL/SPI MOSI functions.
16 P0.5 bidirectional GPIO port 0 bit 5 with watch crystal oscillator output (wco.wco_out), SCB1 UART TX and I2C SDA/SPI MISO functions.
17 P0.6 bidirectional GPIO port 0 bit 6 with external clock input (srss.ext_clk), SCB1 UART CTS and SPI clock functions.
18 XRES input External reset input to the device.
19 VCCD power_out Regulated digital supply (1.8 V ±5%); must be bypassed to ground with a 0.1 µF X5R or better ceramic capacitor and not connected to anything else in the 1.8 V to 5.5 V supply mode.
20 VSSD power_in Ground pin for the digital section.
21 VDD power_in Power supply to all sections of the chip, 1.8 V to 5.5 V (or 1.8 V ±5% when externally regulated).
22 VSSA power_in Ground pin for the analog section.
23 P1.2 bidirectional GPIO port 1 bit 2 with TCPWM line[3], SCB0 UART CTS, tcpwm.tr_in[2] and SCB0 SPI clock functions.
24 P1.3 bidirectional GPIO port 1 bit 3 with TCPWM line_compl[3], SCB0 UART RTS, tcpwm.tr_in[3] and SCB0 SPI select0 functions.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package QFN-24-EP(4x4)
Category Single Chip Microcomputer/Microcontroller
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDDD_ABS -0.5 6 V 21
Direct digital core voltage input relative to VSS VCCD_ABS -0.5 1.95 V 21
GPIO voltage VGPIO_ABS -0.5 6 V VDD + 0.5 as printed (max given as VDD + 0.5) 21
Maximum current per GPIO IGPIO_ABS -25 25 mA 21
GPIO injection current IGPIO_injection -0.5 0.5 mA Max for VIH > VDDD, and Min for VIL < VSS; current injected per pin 21
ESD human body model ESD_HBM 2200 V 21
ESD charged device model ESD_CDM 500 V 21
Pin current for latch-up LU -140 140 mA 21
Power supply input voltage VDD 1.8 5.5 V Internally regulated supply 22
Power supply input voltage (VCCD = VDD = VDDA) VDD 1.71 1.89 V Internally unregulated supply 22
Active mode current, CPU at 6 MHz IDD5 1.2 2 mA Execute from flash; CPU at 6 MHz; VDD = 1.8 V to 5.5 V 22
Active mode current, CPU at 24 MHz IDD8 2.4 4 mA Execute from flash; CPU at 24 MHz; VDD = 1.8 V to 5.5 V 22
Active mode current, CPU at 48 MHz IDD11 4.6 5.9 mA Execute from flash; CPU at 48 MHz; VDD = 1.8 V to 5.5 V 22
Sleep current, 6 MHz (regulator on) IDD17 1.1 1.6 mA I2C wakeup, WDT, and comparators on; 6 MHz; VDDD = 1.8 V to 5.5 V 22
Sleep current, 12 MHz (regulator on) IDD20 1.4 1.9 mA I2C wakeup, WDT, and comparators on; 12 MHz; VDDD = 1.8 V to 5.5 V 22
Sleep current, 6 MHz (regulator bypassed) IDD23 0.7 0.9 mA I2C wakeup, WDT, and comparators on; 6 MHz; VDDD = 1.71 V to 1.89 V 22
Sleep current, 12 MHz (regulator bypassed) IDD23A 0.9 1.1 mA I2C wakeup, WDT, and comparators on; 12 MHz; VDDD = 1.71 V to 1.89 V 22
Deep Sleep current, 1.8 V to 3.6 V IDD26 2.5 60 µA I2C wakeup and WDT on; VDD = 1.8 V to 3.6 V (Regulator on) 22
Deep Sleep current, 3.6 V to 5.5 V IDD29 2.5 60 µA I2C wakeup and WDT on; VDD = 3.6 V to 5.5 V (Regulator on) 22
Deep Sleep current, regulator bypassed IDD32 2.5 60 µA I2C wakeup and WDT on; VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed) 22
Supply current while XRES asserted IDD_XR 2 5 mA 22
Output voltage (for core logic) VCCD 1.8 V 22
External regulator voltage bypass CEFC 0.1 µF X5R ceramic or better 22
Power supply bypass capacitor CEXC 1 µF X5R ceramic or better 22
IMO operating current at 48 MHz IIMO1 250 µA 39
IMO operating current at 24 MHz IIMO2 180 µA 39
IMO frequency variation at 24, 32, and 48 MHz (trimmed) FIMOTOL1 -2 2 % At -40°C to 85°C, for industrial temperature range and original extended industrial range parts 39
IMO startup time TSTARTIMO 7 µs 39
RMS jitter at 24 MHz TJITRMSIMO2 145 ps 39
ILO operating current IILO1 0.3 1.05 µA 40
ILO startup time TSTARTILO1 2 ms 40
ILO duty cycle TILODUTY 40 50 60 % 40
ILO frequency range FILOTRIM1 20 40 80 kHz 40
WCO crystal frequency FWCO 32.768 kHz 40
WCO frequency tolerance FTOL 50 250 ppm With 20-ppm crystal 40
WCO equivalent series resistance ESR 50 kΩ 40
WCO drive level PD 1 µW 40
WCO startup time TSTART 500 ms 40
WCO crystal load capacitance CL 6 12.5 pF 40
WCO crystal shunt capacitance C0 1.35 pF 40
WCO operating current (high power mode) IWCO1 8 µA 40
WCO operating current (low power mode) IWCO2 1 µA 40
External clock input frequency ExtClkFreq 0 48 MHz 41
External clock duty cycle ExtClkDuty 45 55 % Measured at VDD/2 41
System clock source switching time TCLKSWITCH 3 4 Periods 41
Max delay added by Smart I/O in Bypass Mode PRG_BYPASS 1.6 ns 41
Operating ambient temperature TA -40 25 105 °C 44
Operating junction temperature TJ -40 125 °C 44
Package thermal resistance θJA TJA 21.7 °C/W 24L QFN 44
Package thermal resistance θJC TJC 5.6 °C/W 24L QFN 44

CAD (KiCad official)

  • Symbol: CY8C4025LQI-S401T
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: cy8c4025lqi-s401t-etched.step / cy8c4025lqi-s401t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4025lqi-s401t.step / cy8c4025lqi-s401t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (58 pp, sha256 493ab905a29a5d98, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF