CY8C4014LQI-421T

{
  "slug": "cy8c4014lqi-421t",
  "version": "0.1.0",
  "type": "component",
  "description": "Infineon Cypress Semicon Microcontrollers (MCU/MPU/SOC), QFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "cy8c4014lqi-421t",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cy8c4014lqi-421t.kicad_sym",
    "cy8c4014lqi-421t.kicad_mod",
    "cy8c4014lqi-421t.glb",
    "cy8c4014lqi-421t.step",
    "cy8c4014lqi-421t.lbr",
    "docs/hero.png",
    "docs/cy8c4014lqi-421t-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cy8c4014lqi-421t-hero.glb",
    "cy8c4014lqi-421t-hero.overlay.json",
    "cy8c4014lqi-421t-etched.glb"
  ],
  "component": {
    "mpn": "CY8C4014LQI-421T",
    "manufacturer": "Infineon Cypress Semicon",
    "package": "QFN-16-EP(3x3)",
    "pin_count": 17,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontrollers (MCU/MPU/SOC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883582991405056",
    "parts": {
      "symbol": "cy8c4014lqi-421t.kicad_sym",
      "footprint": "cy8c4014lqi-421t.kicad_mod",
      "model_3d": "cy8c4014lqi-421t-hero.glb",
      "model_3d_plain": "cy8c4014lqi-421t-etched.glb",
      "model_3d_step": "cy8c4014lqi-421t-etched.step",
      "model_3d_step_plain": "cy8c4014lqi-421t.step",
      "lbr": "cy8c4014lqi-421t.lbr"
    },
    "distributor_links": {
      "lcsc": "C382039",
      "digikey": "448-CY8C4014LQI-421TTR-ND",
      "mouser": "727-CY8C4014LQI-421T"
    },
    "distributor_check": {
      "checked_at": "2026-10-19T07:46:57Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "448-CY8C4014LQI-421TTR-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "727-CY8C4014LQI-421T",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "P0.1/TRIN1/CMPO_0",
        "type": "bidirectional",
        "description": "Port 0 GPIO that can also serve as a CapSense sense/shield pin on the AMUXBUS, TCPWM trigger input TRIN1, or comparator output CMPO_0 (Sense Comp Out)."
      },
      {
        "number": "2",
        "name": "P0.2/TRIN2",
        "type": "bidirectional",
        "description": "Port 0 GPIO that can also serve as a CapSense sense/shield pin on the AMUXBUS or as TCPWM trigger input TRIN2."
      },
      {
        "number": "3",
        "name": "P0.4/TRIN4/CMPO_0/EXT_CLK",
        "type": "bidirectional",
        "description": "Port 0 GPIO that can also serve as TCPWM trigger input TRIN4, comparator output CMPO_0, external clock EXT_CLK, or CMOD capacitor connection."
      },
      {
        "number": "4",
        "name": "VCCD",
        "type": "power_out",
        "description": "Regulated digital supply of 1.8 V ±5%; in unregulated external supply mode it must be bypassed to ground with a 0.1 µF X5R ceramic or better capacitor, and in regulated external supply mode it is shorted to VDD."
      },
      {
        "number": "5",
        "name": "VDDIO",
        "type": "power_in",
        "description": "Separate voltage domain supply for P3.0, P3.1 and P3.2, which can run at a different voltage than VDD (for example 1.8 V with VDD at 3.3 V) with 1.71 V < VDDIO as shown in the power figures."
      },
      {
        "number": "6",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply for both analog and digital sections, 1.8 V to 5.5 V in unregulated external supply mode or 1.71 V to 1.89 V in regulated external supply mode, where VDD must never exceed 1.89 V in any condition including flash programming."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin."
      },
      {
        "number": "8",
        "name": "P0.6",
        "type": "bidirectional",
        "description": "Port 0 GPIO that can also serve as a CapSense sense or shield pin connected to AMUXBUS A or B."
      },
      {
        "number": "9",
        "name": "P1.1/OUT0",
        "type": "bidirectional",
        "description": "Port 1 GPIO that can also serve as TCPWM PWM output OUT0."
      },
      {
        "number": "10",
        "name": "P1.2/SCL",
        "type": "bidirectional",
        "description": "Port 1 GPIO used as I2C clock (SCL) in open-drain mode, compatible with I2C Standard-mode and Fast-mode (up to 400 kbps), and GPIO cells are not overvoltage tolerant."
      },
      {
        "number": "11",
        "name": "P1.3/SDA",
        "type": "bidirectional",
        "description": "Port 1 GPIO used as I2C data (SDA) in open-drain mode, compatible with I2C Standard-mode and Fast-mode, and GPIO cells are not overvoltage tolerant."
      },
      {
        "number": "12",
        "name": "P1.6/OVF0/UND0/nOUT0/CMPO_0",
        "type": "bidirectional",
        "description": "Port 1 GPIO that can also serve as TCPWM OVF0, UND0, complement output nOUT0, or comparator output CMPO_0 for internal reset, and it must not have a load to ground during POR (should be an output)."
      },
      {
        "number": "13",
        "name": "P1.7/MATCH/EXT_CLK",
        "type": "bidirectional",
        "description": "Port 1 GPIO that can also serve as match output MATCH or external clock EXT_CLK."
      },
      {
        "number": "14",
        "name": "P3.0/SDA/SWD_IO",
        "type": "bidirectional",
        "description": "Port 3 GPIO in the VDDIO voltage domain that can also serve as I2C data (SDA) or SWD I/O."
      },
      {
        "number": "15",
        "name": "P3.1/SCL/SWD_CLK",
        "type": "bidirectional",
        "description": "Port 3 GPIO in the VDDIO voltage domain that can also serve as I2C clock (SCL) or SWD clock."
      },
      {
        "number": "16",
        "name": "P3.2",
        "type": "bidirectional",
        "description": "Port 3 GPIO in the VDDIO voltage domain that can also serve as TCPWM PWM output OUT0."
      },
      {
        "number": "17",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The ordering table text is garbled. Using the column layout, CY8C4014LQI-421 (LQ = QFN) maps to the ; Table 1 prints pin 4 as 'VCC' for the 16-pin QFN, but Figure 6 and the power section label this pin ; Pin 4 type is set to power_out because the datasheet says VCCD is the internal regulator output in u",
          "exposed pad 17 added from the footprint"
        ],
        "pages_sent": 17,
        "cost_usd": 0.1039,
        "at": "2026-10-19T07:46:42"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883582991405056",
        "pages": 35,
        "sha256": "d8f010e7d78eade9",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 17,
        "described": 17,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cy8c4014lqi-421t.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          3.0,
          3.0,
          0.785
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3eb81ffac423a66cdcfead8efe56401da171edaf1f2257049aad7b2d3900f6c8",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cy8c4014lqi-421t-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          3.0,
          3.0,
          0.785
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "266e3cd807a8351c1934e6ed910341927dba5dcada712bd924c0eaca4412c850",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}