component
CY8C4014LQI-421T
Public Made by Adomby adom
Infineon Cypress Semicon Microcontrollers (MCU/MPU/SOC), QFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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|---|---|
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| cy8c4014lqi-421t-etched.glb | 7d ago |
| cy8c4014lqi-421t-etched.step | 7d ago |
| cy8c4014lqi-421t-hero.glb | 7d ago |
| cy8c4014lqi-421t-hero.overlay.json | 7d ago |
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| README.md | 7d ago |
CY8C4014LQI-421T
Infineon Cypress Semicon · Microcontrollers (MCU/MPU/SOC) · QFN-16-EP(3x3)
CY8C4014LQI-421T from Infineon Cypress Semicon, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.1/TRIN1/CMPO_0 | bidirectional | Port 0 GPIO that can also serve as a CapSense sense/shield pin on the AMUXBUS, TCPWM trigger input TRIN1, or comparator output CMPO_0 (Sense Comp Out). |
| 2 | P0.2/TRIN2 | bidirectional | Port 0 GPIO that can also serve as a CapSense sense/shield pin on the AMUXBUS or as TCPWM trigger input TRIN2. |
| 3 | P0.4/TRIN4/CMPO_0/EXT_CLK | bidirectional | Port 0 GPIO that can also serve as TCPWM trigger input TRIN4, comparator output CMPO_0, external clock EXT_CLK, or CMOD capacitor connection. |
| 4 | VCCD | power_out | Regulated digital supply of 1.8 V ±5%; in unregulated external supply mode it must be bypassed to ground with a 0.1 µF X5R ceramic or better capacitor, and in regulated external supply mode it is shorted to VDD. |
| 5 | VDDIO | power_in | Separate voltage domain supply for P3.0, P3.1 and P3.2, which can run at a different voltage than VDD (for example 1.8 V with VDD at 3.3 V) with 1.71 V < VDDIO as shown in the power figures. |
| 6 | VDD | power_in | Power supply for both analog and digital sections, 1.8 V to 5.5 V in unregulated external supply mode or 1.71 V to 1.89 V in regulated external supply mode, where VDD must never exceed 1.89 V in any condition including flash programming. |
| 7 | VSS | power_in | Ground pin. |
| 8 | P0.6 | bidirectional | Port 0 GPIO that can also serve as a CapSense sense or shield pin connected to AMUXBUS A or B. |
| 9 | P1.1/OUT0 | bidirectional | Port 1 GPIO that can also serve as TCPWM PWM output OUT0. |
| 10 | P1.2/SCL | bidirectional | Port 1 GPIO used as I2C clock (SCL) in open-drain mode, compatible with I2C Standard-mode and Fast-mode (up to 400 kbps), and GPIO cells are not overvoltage tolerant. |
| 11 | P1.3/SDA | bidirectional | Port 1 GPIO used as I2C data (SDA) in open-drain mode, compatible with I2C Standard-mode and Fast-mode, and GPIO cells are not overvoltage tolerant. |
| 12 | P1.6/OVF0/UND0/nOUT0/CMPO_0 | bidirectional | Port 1 GPIO that can also serve as TCPWM OVF0, UND0, complement output nOUT0, or comparator output CMPO_0 for internal reset, and it must not have a load to ground during POR (should be an output). |
| 13 | P1.7/MATCH/EXT_CLK | bidirectional | Port 1 GPIO that can also serve as match output MATCH or external clock EXT_CLK. |
| 14 | P3.0/SDA/SWD_IO | bidirectional | Port 3 GPIO in the VDDIO voltage domain that can also serve as I2C data (SDA) or SWD I/O. |
| 15 | P3.1/SCL/SWD_CLK | bidirectional | Port 3 GPIO in the VDDIO voltage domain that can also serve as I2C clock (SCL) or SWD clock. |
| 16 | P3.2 | bidirectional | Port 3 GPIO in the VDDIO voltage domain that can also serve as TCPWM PWM output OUT0. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Cypress Semicon |
| Package | QFN-16-EP(3x3) |
| Category | Embedded Processors & Controllers |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Digital supply voltage relative to VSS | VDD_ABS | -0.5 | 6 | V | 14 | ||
| Direct digital core voltage input relative to VSS | VCCD_ABS | -0.5 | 1.95 | V | 14 | ||
| Maximum current per GPIO | IGPIO_ABS | -25 | 25 | mA | 14 | ||
| GPIO injection current | IGPIO_injection | -0.5 | 0.5 | mA | Current injected per pin | 14 | |
| Electrostatic discharge human body model | ESD_HBM | 2200 | V | 14 | |||
| Electrostatic discharge charged device model | ESD_CDM | 500 | V | 14 | |||
| Pin current for latch-up | LU | -140 | 140 | mA | 14 | ||
| Power supply input voltage | VDD | 1.8 | 5.5 | V | With regulator enabled | 14 | |
| Power supply input voltage (VCCD = VDD) | VDD | 1.71 | 1.89 | V | Internally unregulated supply | 14 | |
| VDDIO domain supply | VDDIO | 1.71 | V | 14 | |||
| Execute from flash; CPU at 6 MHz (Active mode) | IDD5 | 2 | 2.85 | mA | Active Mode, VDD = 1.8 to 5.5 V | 14 | |
| Execute from flash; CPU at 12 MHz (Active mode) | IDD8 | 3.2 | 3.75 | mA | Active Mode, VDD = 1.8 to 5.5 V | 14 | |
| Execute from flash; CPU at 16 MHz (Active mode) | IDD11 | 4 | 4.5 | mA | Active Mode, VDD = 1.8 to 5.5 V | 14 | |
| I2C wakeup and WDT on (Deep Sleep, regulator on) | IDD26 | 2.5 | 8.2 | µA | Deep Sleep Mode, VDD = 1.8 to 3.6 V (Regulator on) | 14 | |
| I2C wakeup and WDT on (Deep Sleep, regulator on) | IDD29 | 2.5 | 12 | µA | Deep Sleep Mode, VDD = 3.6 to 5.5 V (Regulator on) | 15 | |
| I2C wakeup and WDT on (Deep Sleep, regulator bypassed) | IDD32 | 2.5 | 9.2 | µA | Deep Sleep Mode, VDD = VCCD = 1.71 to 1.89 V (Regulator bypassed) | 15 | |
| Supply current while XRES asserted | IDD_XR | 2 | 5 | mA | 15 | ||
| CPU frequency | FCPU | 16 | MHz | 1.71 VDD 5.5 | 15 | ||
| External clock input frequency | ExtClkFreq | 0 | 16 | MHz | 22 | ||
| Duty cycle | ExtClkDuty | 45 | 55 | % | measured at VDD/2 | 22 | |
| System clock source switching time | TCLKSWITCH | 3 | 4 | Periods | 22 | ||
| Input voltage high threshold (LVTTL input, VDD ≥ 2.7 V) | VIH | 2 | V | LVTTL input, VDD ≥ 2.7 V | 15 | ||
| Input voltage low threshold (LVTTL input, VDD ≥ 2.7 V) | VIL | 0.8 | V | LVTTL input, VDD ≥ 2.7 V | 15 | ||
| Output voltage low level | VOL | 0.6 | V | IOL = 4 mA at 1.8 V VDD | 15 | ||
| Output voltage low level | VOL | 0.4 | V | IOL = 3 mA at 3 V VDD | 15 | ||
| Pull-up resistor | RPULLUP | 3.5 | 5.6 | 8.5 | kΩ | 15 | |
| Pull-down resistor | RPULLDOWN | 3.5 | 5.6 | 8.5 | kΩ | 15 | |
| Input leakage current (absolute value) | IIL | 2 | nA | 25 °C, VDD = 3.0 V | 15 | ||
| Input capacitance | CIN | 3 | 7 | pF | 15 |
CAD (KiCad official)
- Symbol:
CY8C4014LQI-421T - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
cy8c4014lqi-421t-etched.step/cy8c4014lqi-421t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cy8c4014lqi-421t.step/cy8c4014lqi-421t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Cypress Semicon datasheet (35 pp, sha256
d8f010e7d78eade9, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).