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CY7C68013A-56LTXC

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Infineon Cypress Semicon Microcontrollers (MCU/MPU/SOC), QFN-56-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY7C68013A-56LTXC

Infineon Cypress Semicon · Microcontrollers (MCU/MPU/SOC) · QFN-56-EP(8x8)

CY7C68013A-56LTXC from Infineon Cypress Semicon, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RDY0/SLRD input GPIF ready input RDY0; SLRD is the input-only slave FIFO read strobe with programmable polarity (FIFOPINPOLAR.3).
2 RDY1/SLWR input GPIF ready input RDY1; SLWR is the input-only slave FIFO write strobe with programmable polarity (FIFOPINPOLAR.2).
3 AVCC power_in Analog VCC; connect to a 3.3V power source to supply the analog section of the chip.
4 XTALOUT output Crystal output for a 24 MHz parallel-resonant fundamental-mode crystal with load capacitor to GND; leave open if an external clock drives XTALIN.
5 XTALIN input Crystal input for a 24 MHz parallel-resonant crystal, or a 3.3V square-wave 24 MHz external clock.
6 AGND power_in Analog ground; connect to ground with as short a path as possible.
7 AVCC power_in Analog VCC; connect to a 3.3V power source to supply the analog section of the chip.
8 DPLUS bidirectional USB D+ signal; connect to the USB D+ signal.
9 DMINUS bidirectional USB D- signal; connect to the USB D- signal.
10 AGND power_in Analog ground; connect to ground with as short a path as possible.
11 VCC power_in VCC; connect to a 3.3V power source.
12 GND power_in Ground.
13 IFCLK bidirectional Interface clock for slave FIFO and GPIF timing, which can be configured as a 30/48 MHz output when internally clocked; on CY7C68015A/16A this pin is PE0 instead.
14 RESERVED input Reserved; connect to ground.
15 SCL bidirectional Clock for the I2C interface; connect to VCC with a 2.2K resistor even if no I2C peripheral is attached.
16 SDA bidirectional Data for the I2C compatible interface; connect to VCC with a 2.2K resistor even if no I2C compatible peripheral is attached.
17 VCC power_in VCC; connect to a 3.3V power source.
18 PB0/FD0 bidirectional Port B bit 0 (PB0) or FIFO/GPIF data bus bit FD[0], selected by IFCONFIG[1..0].
19 PB1/FD1 bidirectional Port B bit 1 (PB1) or FIFO/GPIF data bus bit FD[1], selected by IFCONFIG[1..0].
20 PB2/FD2 bidirectional Port B bit 2 (PB2) or FIFO/GPIF data bus bit FD[2], selected by IFCONFIG[1..0].
21 PB3/FD3 bidirectional Port B bit 3 (PB3) or FIFO/GPIF data bus bit FD[3], selected by IFCONFIG[1..0].
22 PB4/FD4 bidirectional Port B bit 4 (PB4) or FIFO/GPIF data bus bit FD[4], selected by IFCONFIG[1..0].
23 PB5/FD5 bidirectional Port B bit 5 (PB5) or FIFO/GPIF data bus bit FD[5], selected by IFCONFIG[1..0].
24 PB6/FD6 bidirectional Port B bit 6 (PB6) or FIFO/GPIF data bus bit FD[6], selected by IFCONFIG[1..0].
25 PB7/FD7 bidirectional Port B bit 7 (PB7) or FIFO/GPIF data bus bit FD[7], selected by IFCONFIG[1..0].
26 GND power_in Ground.
27 VCC power_in VCC; connect to a 3.3V power source.
28 GND power_in Ground.
29 CTL0/FLAGA tri_state GPIF control output CTL0; alternate function is FLAGA, a programmable slave FIFO status flag that defaults to the FIFO selected by FIFOADR[1:0].
30 CTL1/FLAGB tri_state GPIF control output CTL1; alternate function is FLAGB, a programmable slave FIFO status flag that defaults to FULL for the FIFO selected by FIFOADR[1:0].
31 CTL2/FLAGC tri_state GPIF control output CTL2; alternate function is FLAGC, a programmable slave FIFO status flag that defaults to EMPTY for the FIFO selected by FIFOADR[1:0].
32 VCC power_in VCC; connect to a 3.3V power source.
33 PA0/INT0# bidirectional Port A bit 0 (PA0) or active-LOW 8051 INT0 interrupt input, which is edge triggered (IT0 = 1) or level triggered (IT0 = 0).
34 PA1/INT1# bidirectional Port A bit 1 (PA1) or active-LOW 8051 INT1 interrupt input, which is edge triggered (IT1 = 1) or level triggered (IT1 = 0).
35 PA2/SLOE bidirectional Port A bit 2 (PA2) or SLOE, an input-only slave FIFO output enable with programmable polarity (FIFOPINPOLAR.4).
36 PA3/WU2 bidirectional Port A bit 3 (PA3) or WU2, an alternate USB wakeup source enabled by WU2EN (WAKEUP.1) with polarity set by WU2POL (WAKEUP.4).
37 PA4/FIFOADR0 bidirectional Port A bit 4 (PA4) or FIFOADR0, an input-only address select for the slave FIFOs.
38 PA5/FIFOADR1 bidirectional Port A bit 5 (PA5) or FIFOADR1, an input-only address select for the slave FIFOs.
39 PA6/PKTEND bidirectional Port A bit 6 (PA6) or PKTEND, an input that commits FIFO packet data to the endpoint, with polarity programmable via FIFOPINPOLAR.5.
40 PA7/FLAGD/SLCS# bidirectional Port A bit 7 (PA7), or FLAGD (programmable slave FIFO status flag), or SLCS#, which gates all other slave FIFO enable/strobes.
41 GND power_in Ground.
42 RESET# input Active-LOW reset that resets the entire chip.
43 VCC power_in VCC; connect to a 3.3V power source.
44 WAKEUP input USB wakeup; when the 8051 is suspended, asserting this pin starts the oscillator and interrupts the 8051, and holding it asserted inhibits suspend; polarity is programmable (WAKEUP.4).
45 PD0/FD8 bidirectional Port D bit 0 (PD0) or FIFO/GPIF data bus bit FD[8], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
46 PD1/FD9 bidirectional Port D bit 1 (PD1) or FIFO/GPIF data bus bit FD[9], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
47 PD2/FD10 bidirectional Port D bit 2 (PD2) or FIFO/GPIF data bus bit FD[10], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
48 PD3/FD11 bidirectional Port D bit 3 (PD3) or FIFO/GPIF data bus bit FD[11], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
49 PD4/FD12 bidirectional Port D bit 4 (PD4) or FIFO/GPIF data bus bit FD[12], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
50 PD5/FD13 bidirectional Port D bit 5 (PD5) or FIFO/GPIF data bus bit FD[13], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
51 PD6/FD14 bidirectional Port D bit 6 (PD6) or FIFO/GPIF data bus bit FD[14], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
52 PD7/FD15 bidirectional Port D bit 7 (PD7) or FIFO/GPIF data bus bit FD[15], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
53 GND power_in Ground.
54 CLKOUT tri_state CLKOUT 12/24/48 MHz clock phase locked to the 24 MHz input, which the 8051 may three-state via CPUCS.1; on CY7C68015A/16A this pin is PE1, a bidirectional I/O port pin.
55 VCC power_in VCC; connect to a 3.3V power source.
56 GND power_in Ground.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Infineon Cypress Semicon
Package QFN-56-EP(8x8)
Category Embedded Processors & Controllers
Pins 57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Supply Voltage VCC 3 3.3 3.6 V 37
VCC Ramp Up 200 μs 0 to 3.3V 37
Input HIGH Voltage VIH 2 5.25 V 37
Input LOW Voltage VIL -0.5 0.8 V 37
Crystal Input HIGH Voltage VIH_X 2 5.25 V 37
Crystal Input LOW Voltage VIL_X -0.5 0.8 V 37
Input Leakage Current II -10 10 μA 0< VIN < VCC 37
Output Voltage HIGH VOH 2.4 V IOUT = 4 mA 37
Output LOW Voltage VOL 0.4 V IOUT = -4 mA 37
Input Pin Capacitance (except D+/D-) CIN 10 pF Except D+/D- 37
Input Pin Capacitance (D+/D-) CIN 15 pF D+/D- 37
Suspend Current (connected) ISUSP 300 380 μA Connected; note 16: measured at Max VCC, 25°C 37
Suspend Current (disconnected, CY7C68013/CY7C68015 row) ISUSP 0.3 1 mA CY7C68013/CY7C68015 Disconnected; note 16: measured at Max VCC, 25°C 37
Supply Current (8051 running, USB HS) ICC 50 85 mA 8051 running, connected to USB HS 37
Supply Current (8051 running, USB FS) ICC 35 65 mA 8051 running, connected to USB FS 37
Reset Time after Valid Power TRESET 5 mS VCC min = 3.0V 37
Pin Reset after powered on 200 μS 37
Storage Temperature -65 150 °C 36
Ambient Temperature with Power Supplied (Commercial) 0 70 °C 36
Supply Voltage to Ground Potential -0.5 4 V 36
DC Input Voltage to Any Input Pin 5.25 V Note 15: do not power I/O with chip power off 36
DC Voltage Applied to Outputs in High Z State -0.5 V Maximum printed as VCC + 0.5V 36
Power Dissipation 300 mW 36
Static Discharge Voltage 2000 V Printed as >2000V 36
Ambient Temperature Under Bias (Commercial) TA 0 70 °C Commercial 36
Oscillator or Crystal Frequency Tolerance FOSC -10 10 ppm 24 MHz ± 10 ppm, parallel resonant 36
Oscillator or Crystal Frequency FOSC 24 MHz Parallel resonant 36
Thermal resistance junction to case, 56 QFN θJc 10.6 °C/W Table 13, 56 QFN, θa = 70 °C 36
Thermal resistance case to ambient, 56 QFN θCa 14.6 °C/W Table 13, 56 QFN, θa = 70 °C 36
Thermal resistance junction to ambient, 56 QFN θJa 25.2 °C/W Table 13, 56 QFN (θJc + θCa), θa = 70 °C 36

CAD (KiCad official)

  • Symbol: CY7C68013A-56LTXC
  • Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • 3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: cy7c68013a-56ltxc-etched.step / cy7c68013a-56ltxc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy7c68013a-56ltxc.step / cy7c68013a-56ltxc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Cypress Semicon datasheet (62 pp, sha256 d1cbe447c12a74fb, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF