CY74FCT373TSOC from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE	input	Output enable input: when OE is low the bus outputs show the latched data, and when OE is high the outputs are in the high-impedance state.
2	O0	tri_state	3-state output 0 of the latch, which is high-impedance when OE is high and drives the bus when OE is low, with a CY74FCT373T rating of 64-mA sink and 32-mA source current.
3	D0	input	Data input 0 to the latch, which must meet the setup and hold times relative to the rising edge of LE (setup 2 ns, hold 1.5 ns).
4	D1	input	Data input 1 to the latch, which must meet the setup and hold times relative to the rising edge of LE (setup 2 ns, hold 1.5 ns).
5	O1	tri_state	3-state output 1 of the latch, which is high-impedance when OE is high and drives the bus when OE is low, with a CY74FCT373T rating of 64-mA sink and 32-mA source current.
6	O2	tri_state	3-state output 2 of the latch, which is high-impedance when OE is high and drives the bus when OE is low, with a CY74FCT373T rating of 64-mA sink and 32-mA source current.
7	D2	input	Data input 2 to the latch, which must meet the setup and hold times relative to the rising edge of LE (setup 2 ns, hold 1.5 ns).
8	D3	input	Data input 3 to the latch, which must meet the setup and hold times relative to the rising edge of LE (setup 2 ns, hold 1.5 ns).
9	O3	tri_state	3-state output 3 of the latch, which is high-impedance when OE is high and drives the bus when OE is low, with a CY74FCT373T rating of 64-mA sink and 32-mA source current.
10	GND	power_in	Ground reference for the device.
11	LE	input	Latch enable input: when LE is high the latches are transparent to the data, and data is latched when LE transitions from high to low.
12	O4	tri_state	3-state output 4 of the latch, which is high-impedance when OE is high and drives the bus when OE is low, with a CY74FCT373T rating of 64-mA sink and 32-mA source current.
13	D4	input	Data input 4 to the latch, which must meet the setup and hold times relative to the rising edge of LE (setup 2 ns, hold 1.5 ns).
14	D5	input	Data input 5 to the latch, which must meet the setup and hold times relative to the rising edge of LE (setup 2 ns, hold 1.5 ns).
15	O5	tri_state	3-state output 5 of the latch, which is high-impedance when OE is high and drives the bus when OE is low, with a CY74FCT373T rating of 64-mA sink and 32-mA source current.
16	O6	tri_state	3-state output 6 of the latch, which is high-impedance when OE is high and drives the bus when OE is low, with a CY74FCT373T rating of 64-mA sink and 32-mA source current.
17	D6	input	Data input 6 to the latch, which must meet the setup and hold times relative to the rising edge of LE (setup 2 ns, hold 1.5 ns).
18	D7	input	Data input 7 to the latch, which must meet the setup and hold times relative to the rising edge of LE (setup 2 ns, hold 1.5 ns).
19	O7	tri_state	3-state output 7 of the latch, which is high-impedance when OE is high and drives the bus when OE is low, with a CY74FCT373T rating of 64-mA sink and 32-mA source current.
20	VCC	power_in	Supply voltage, recommended range 4.75 V to 5.25 V (nominal 5 V) for the CY74FCT373T.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-20-300mil
Category	Logic
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	4.75	5	5.25	V		3
High-level input voltage	VIH	2			V		3
Low-level input voltage	VIL			0.8	V		3
High-level output current	IOH			-32	mA		3
Low-level output current	IOL			64	mA		3
Operating free-air temperature	TA	-40		85	°C		3
Supply voltage range to ground potential		-0.5		7	V		3
DC input voltage range		-0.5		7	V		3
DC output voltage range		-0.5		7	V		3
DC output current (maximum sink current/pin)				120	mA		3
Ambient temperature range with power applied	TA	-65		135	°C		3
Storage temperature range	Tstg	-65		150	°C		3
Pulse duration, LE high	tw	6			ns	see Figure 1	6
Setup time, data before LE↑	tsu	2			ns	see Figure 1	6
Hold time, data after LE↑	th	1.5			ns	see Figure 1	6
Propagation delay D to O (low-to-high)	tPLH	1.5		8	ns	see Figure 1	6
Propagation delay D to O (high-to-low)	tPHL	1.5		8	ns	see Figure 1	6
Propagation delay LE to O (low-to-high)	tPLH	2		13	ns	see Figure 1	6
Propagation delay LE to O (high-to-low)	tPHL	2		13	ns	see Figure 1	6
Enable time OE to O (high)	tPZH	1.5		12	ns	see Figure 1	6
Enable time OE to O (low)	tPZL	1.5		12	ns	see Figure 1	6
Disable time OE to O (high)	tPHZ	1.5		7.5	ns	see Figure 1	6
Disable time OE to O (low)	tPLZ	1.5		7.5	ns	see Figure 1	6
High-level output voltage	VOH	2.4	3.3		V	VCC = 4.75 V, IOH = -15 mA	4
High-level output voltage	VOH	2			V	VCC = 4.75 V, IOH = -32 mA	4
Low-level output voltage	VOL		0.3	0.55	V	VCC = 4.75 V, IOL = 64 mA	4
Input clamp voltage	VIK		-0.7	-1.2	V	VCC = 4.75 V, IIN = -18 mA	4
Input current	II			5	µA	VCC = 5.25 V, VIN = VCC	4
High-level input current	IIH	-1		1	µA	VCC = 5.25 V, VIN = 2.7 V	4
Low-level input current	IIL	-1		1	µA	VCC = 5.25 V, VIN = 0.5 V	4
High-level off-state output current	IOZH			10	µA	VCC = 5.25 V, VOUT = 2.7 V	4
Low-level off-state output current	IOZL			-10	µA	VCC = 5.25 V, VOUT = 0.5 V	4
Short-circuit output current	IOS	-60	-120	-225	mA	VCC = 5.25 V, VOUT = 0 V	4
Power-off leakage current	Ioff	-1		1	µA	VCC = 0 V, VOUT = 4.5 V	4
Quiescent supply current	ICC		0.1	0.2	mA	VCC = 5.25 V, VIN ≤ 0.2 V, VIN ≥ VCC, 0.2 V	4
Supply current per TTL high input	ΔICC		0.5	2	mA	VCC = 5.25 V, VIN = 3.4 V, f1 = 0, Outputs open	4
Dynamic current per input transition	ICCD		0.06	0.12	mA/MHz	VCC = 5.25 V, Outputs open, one input switching at 50% duty cycle, OE = GND	5
Total supply current, one bit switching at 10 MHz	IC		0.7	1.4	mA	VCC = 5.25 V, one bit switching at f1 = 10 MHz, VIN ≤ 0.2 V or VIN ≥ VCC, 0.2 V	5
Total supply current, one bit switching at 50% duty cycle	IC		1	2.4	mA	VCC = 5.25 V, Outputs open, one bit at 50% duty cycle, VIN = 3.4 V or GND, OE = GND, LE = VCC	5
Total supply current, eight bits switching at 2.5 MHz	IC		1.3	2.6	mA	VCC = 5.25 V, eight bits switching at f1 = 2.5 MHz, VIN ≤ 0.2 V or VIN ≥ VCC, 0.2 V	5
Total supply current, eight bits switching at 2.5 MHz, TTL inputs	IC		3.3	10.6	mA	VCC = 5.25 V, Outputs open, eight bits at 50% duty cycle, VIN = 3.4 V or GND, OE = GND, LE = VCC	5
Input capacitance	Ci		6	10	pF		5
Output capacitance	Co		8	12	pF		5
Package thermal impedance, junction-to-ambient (SO package)	θJA		58		°C/W	SO package, per JESD 51-7	3

CAD (KiCad official)

Symbol: CY74FCT373TSOC
Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
3D model: SOIC-20-300mil (KiCad packages3D, STEP)
3D model files: cy74fct373tsoc-etched.step / cy74fct373tsoc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy74fct373tsoc.step / cy74fct373tsoc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (13 pp, sha256 826e982302a909bc, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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CY74FCT373TSOC

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