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CY74FCT273ATSOCT

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Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY74FCT273ATSOCT

Texas Instruments · Flip Flops · SOIC-20-300mil

CY74FCT273ATSOCT from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Active-low master reset; a low level forces all Q outputs low regardless of clock or D inputs.
2 Q0 output Registered output of flip-flop 0, loaded from D0 on the low-to-high CP transition and forced low by MR.
3 D0 input Data input to flip-flop 0, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition.
4 D1 input Data input to flip-flop 1, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition.
5 Q1 output Registered output of flip-flop 1, loaded from D1 on the low-to-high CP transition and forced low by MR.
6 Q2 output Registered output of flip-flop 2, loaded from D2 on the low-to-high CP transition and forced low by MR.
7 D2 input Data input to flip-flop 2, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition.
8 D3 input Data input to flip-flop 3, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition.
9 Q3 output Registered output of flip-flop 3, loaded from D3 on the low-to-high CP transition and forced low by MR.
10 GND power_in Ground reference for the device.
11 CP input Common buffered clock; D inputs are transferred to the Q outputs on its low-to-high transition, with a minimum pulse width of 6 ns.
12 Q4 output Registered output of flip-flop 4, loaded from D4 on the low-to-high CP transition and forced low by MR.
13 D4 input Data input to flip-flop 4, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition.
14 D5 input Data input to flip-flop 5, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition.
15 Q5 output Registered output of flip-flop 5, loaded from D5 on the low-to-high CP transition and forced low by MR.
16 Q6 output Registered output of flip-flop 6, loaded from D6 on the low-to-high CP transition and forced low by MR.
17 D6 input Data input to flip-flop 6, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition.
18 D7 input Data input to flip-flop 7, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition.
19 Q7 output Registered output of flip-flop 7, loaded from D7 on the low-to-high CP transition and forced low by MR.
20 VCC power_in Supply pin; the datasheet's recommended supply range for the CY74FCT273T is 4.75 V to 5.25 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: CY74FCT273ATSOCT
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: cy74fct273atsoct-etched.step / cy74fct273atsoct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy74fct273atsoct.step / cy74fct273atsoct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (13 pp, sha256 f862c55b121c0af8, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF