component
CY74FCT273ATSOCT
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# CY74FCT273ATSOCT++**Texas Instruments** · Flip Flops · SOIC-20-300mil++CY74FCT273ATSOCT from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | MR | input | Active-low master reset; a low level forces all Q outputs low regardless of clock or D inputs. |+| 2 | Q0 | output | Registered output of flip-flop 0, loaded from D0 on the low-to-high CP transition and forced low by MR. |+| 3 | D0 | input | Data input to flip-flop 0, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition. |+| 4 | D1 | input | Data input to flip-flop 1, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition. |+| 5 | Q1 | output | Registered output of flip-flop 1, loaded from D1 on the low-to-high CP transition and forced low by MR. |+| 6 | Q2 | output | Registered output of flip-flop 2, loaded from D2 on the low-to-high CP transition and forced low by MR. |+| 7 | D2 | input | Data input to flip-flop 2, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition. |+| 8 | D3 | input | Data input to flip-flop 3, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition. |+| 9 | Q3 | output | Registered output of flip-flop 3, loaded from D3 on the low-to-high CP transition and forced low by MR. |+| 10 | GND | power_in | Ground reference for the device. |+| 11 | CP | input | Common buffered clock; D inputs are transferred to the Q outputs on its low-to-high transition, with a minimum pulse width of 6 ns. |+| 12 | Q4 | output | Registered output of flip-flop 4, loaded from D4 on the low-to-high CP transition and forced low by MR. |+| 13 | D4 | input | Data input to flip-flop 4, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition. |+| 14 | D5 | input | Data input to flip-flop 5, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition. |+| 15 | Q5 | output | Registered output of flip-flop 5, loaded from D5 on the low-to-high CP transition and forced low by MR. |+| 16 | Q6 | output | Registered output of flip-flop 6, loaded from D6 on the low-to-high CP transition and forced low by MR. |+| 17 | D6 | input | Data input to flip-flop 6, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition. |+| 18 | D7 | input | Data input to flip-flop 7, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition. |+| 19 | Q7 | output | Registered output of flip-flop 7, loaded from D7 on the low-to-high CP transition and forced low by MR. |+| 20 | VCC | power_in | Supply pin; the datasheet's recommended supply range for the CY74FCT273T is 4.75 V to 5.25 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-20-300mil |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `CY74FCT273ATSOCT`+- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`+- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)+- 3D model files: `cy74fct273atsoct-etched.step` / `cy74fct273atsoct-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cy74fct273atsoct.step` / `cy74fct273atsoct.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cy74fct273t) (13 pp, sha256 `f862c55b121c0af8`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cy74fct273atsoct-datasheet.pdf)
page.jsonadded+271@@ -0,0 +1,271 @@+{+ "slug": "cy74fct273atsoct",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cy74fct273atsoct",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cy74fct273atsoct.kicad_sym",+ "cy74fct273atsoct.kicad_mod",+ "cy74fct273atsoct.glb",+ "cy74fct273atsoct.step",+ "cy74fct273atsoct.lbr",+ "docs/hero.png",+ "docs/cy74fct273atsoct-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cy74fct273atsoct-hero.glb",+ "cy74fct273atsoct-hero.overlay.json"+ ],+ "component": {+ "mpn": "CY74FCT273ATSOCT",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-20-300mil",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cy74fct273t",+ "parts": {+ "symbol": "cy74fct273atsoct.kicad_sym",+ "footprint": "cy74fct273atsoct.kicad_mod",+ "model_3d": "cy74fct273atsoct-hero.glb",+ "model_3d_plain": "cy74fct273atsoct.glb",+ "model_3d_step": "cy74fct273atsoct-etched.step",+ "model_3d_step_plain": "cy74fct273atsoct.step",+ "lbr": "cy74fct273atsoct.lbr"+ },+ "distributor_links": {+ "lcsc": "C2677797",+ "digikey": "296-28861-2-ND"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T19:32:59Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-28861-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": null,+ "status": "error"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "MR",+ "type": "input",+ "description": "Active-low master reset; a low level forces all Q outputs low regardless of clock or D inputs."+ },+ {+ "number": "2",+ "name": "Q0",+ "type": "output",+ "description": "Registered output of flip-flop 0, loaded from D0 on the low-to-high CP transition and forced low by MR."+ },+ {+ "number": "3",+ "name": "D0",+ "type": "input",+ "description": "Data input to flip-flop 0, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition."+ },+ {+ "number": "4",+ "name": "D1",+ "type": "input",+ "description": "Data input to flip-flop 1, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition."+ },+ {+ "number": "5",+ "name": "Q1",+ "type": "output",+ "description": "Registered output of flip-flop 1, loaded from D1 on the low-to-high CP transition and forced low by MR."+ },+ {+ "number": "6",+ "name": "Q2",+ "type": "output",+ "description": "Registered output of flip-flop 2, loaded from D2 on the low-to-high CP transition and forced low by MR."+ },+ {+ "number": "7",+ "name": "D2",+ "type": "input",+ "description": "Data input to flip-flop 2, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition."+ },+ {+ "number": "8",+ "name": "D3",+ "type": "input",+ "description": "Data input to flip-flop 3, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition."+ },+ {+ "number": "9",+ "name": "Q3",+ "type": "output",+ "description": "Registered output of flip-flop 3, loaded from D3 on the low-to-high CP transition and forced low by MR."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "11",+ "name": "CP",+ "type": "input",+ "description": "Common buffered clock; D inputs are transferred to the Q outputs on its low-to-high transition, with a minimum pulse width of 6 ns."+ },+ {+ "number": "12",+ "name": "Q4",+ "type": "output",+ "description": "Registered output of flip-flop 4, loaded from D4 on the low-to-high CP transition and forced low by MR."+ },+ {+ "number": "13",+ "name": "D4",+ "type": "input",+ "description": "Data input to flip-flop 4, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition."+ },+ {+ "number": "14",+ "name": "D5",+ "type": "input",+ "description": "Data input to flip-flop 5, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition."+ },+ {+ "number": "15",+ "name": "Q5",+ "type": "output",+ "description": "Registered output of flip-flop 5, loaded from D5 on the low-to-high CP transition and forced low by MR."+ },+ {+ "number": "16",+ "name": "Q6",+ "type": "output",+ "description": "Registered output of flip-flop 6, loaded from D6 on the low-to-high CP transition and forced low by MR."+ },+ {+ "number": "17",+ "name": "D6",+ "type": "input",+ "description": "Data input to flip-flop 6, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition."+ },+ {+ "number": "18",+ "name": "D7",+ "type": "input",+ "description": "Data input to flip-flop 7, which needs a 2 ns setup time and 1.5 ns hold time around the low-to-high CP transition."+ },+ {+ "number": "19",+ "name": "Q7",+ "type": "output",+ "description": "Registered output of flip-flop 7, loaded from D7 on the low-to-high CP transition and forced low by MR."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply pin; the datasheet's recommended supply range for the CY74FCT273T is 4.75 V to 5.25 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pinout diagram on page 1 is labelled 'Q OR SO PACKAGE' and is shared by the SSOP (Q) and SOIC (S; The pin numbers were reconstructed from the jumbled text layout. They were cross-checked against the; The recommended operating conditions (page 3) list the 4.75 V to 5.25 V VCC range and the 64 mA / 32"+ ],+ "pages_sent": 13,+ "cost_usd": 0.0861,+ "at": "2026-10-08T19:32:00"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cy74fct273t",+ "pages": 13,+ "sha256": "f862c55b121c0af8",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cy74fct273atsoct.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 12.8,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "59a10b341e6972b31d81802a048060326da627d8b92dcf4263064f4f62ec808e",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cy74fct273atsoct-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 12.8,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "8cfd8e16d5278dd5ab1afb342d6086cb21791c018de96c347b3651ebe15ee7c9",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}