CY22381FXC

{
  "slug": "cy22381fxc",
  "version": "0.1.0",
  "type": "component",
  "description": "SPANSION Clock Generators / Frequency Synthesizers / PLL, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "clock and timing",
    "cy22381fxc",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "cy22381fxc.kicad_sym",
    "cy22381fxc.kicad_mod",
    "cy22381fxc.glb",
    "cy22381fxc.step",
    "cy22381fxc.lbr",
    "docs/hero.png",
    "docs/cy22381fxc-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cy22381fxc-hero.glb",
    "cy22381fxc-hero.overlay.json",
    "cy22381fxc-etched.glb"
  ],
  "component": {
    "mpn": "CY22381FXC",
    "manufacturer": "SPANSION",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Clock and Timing",
    "subcategory": "Clock Generators / Frequency Synthesizers / PLL",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/c23e63fb7796340d3e1a24eb1b9fa62a.pdf",
    "parts": {
      "symbol": "cy22381fxc.kicad_sym",
      "footprint": "cy22381fxc.kicad_mod",
      "model_3d": "cy22381fxc-hero.glb",
      "model_3d_plain": "cy22381fxc-etched.glb",
      "model_3d_step": "cy22381fxc-etched.step",
      "model_3d_step_plain": "cy22381fxc.step",
      "lbr": "cy22381fxc.lbr"
    },
    "distributor_links": {
      "lcsc": "C1535671",
      "digikey": "2156-CY22381FXC-ND",
      "mouser": "727-CY22381FXC"
    },
    "distributor_check": {
      "checked_at": "2026-10-30T22:49:25Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "2156-CY22381FXC-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "727-CY22381FXC",
        "status": "found",
        "lifecycle": "Not Recommended for New Designs"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "CLKC",
        "type": "output",
        "description": "Configurable clock output C, taken from the crosspoint switch through a seven-bit post divider and designed to drive a single-point load of 15 pF total lumped capacitance."
      },
      {
        "number": "2",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device."
      },
      {
        "number": "3",
        "name": "XTALIN",
        "type": "input",
        "description": "Reference crystal input or external reference clock input; the crystal range is 8 to 30 MHz and the external clock range is 1 to 166 MHz for commercial parts (1 to 150 MHz for industrial)."
      },
      {
        "number": "4",
        "name": "XTALOUT",
        "type": "output",
        "description": "Reference crystal feedback; it must be left floating when XTALIN is driven by an external reference clock."
      },
      {
        "number": "5",
        "name": "CLKB",
        "type": "output",
        "description": "Configurable clock output B, taken from the crosspoint switch through a seven-bit post divider whose value is selected by FS, and designed to drive a single-point load of 15 pF total lumped capacitance."
      },
      {
        "number": "6",
        "name": "CLKA",
        "type": "output",
        "description": "Configurable clock output A, taken from the crosspoint switch through a seven-bit post divider whose value is selected by FS, and designed to drive a single-point load of 15 pF total lumped capacitance."
      },
      {
        "number": "7",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply, 3.135 V minimum, 3.3 V typical and 3.465 V maximum."
      },
      {
        "number": "8",
        "name": "FS/SUSPEND/OE/SHUTDOWN",
        "type": "input",
        "description": "General-purpose CMOS input, programmable as frequency select, Suspend control, output enable (all outputs three-state when LOW), or full-chip shutdown (when LOW); its logic-high threshold is 70% of VDD minimum and its logic-low threshold is 30% of VDD maximum."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin types for XTALOUT (output) and XTALIN (input) are inferred from the function descriptions; the d; Voltage, frequency and threshold limits quoted in the descriptions come from the Operating Condition; The datasheet covers CY22381FXC and the NiPdAu lead-finish variant CY223811FXI; the pinout is shared"
        ],
        "pages_sent": 14,
        "cost_usd": 0.0565,
        "at": "2026-10-30T22:49:07"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/c23e63fb7796340d3e1a24eb1b9fa62a.pdf",
        "pages": 14,
        "sha256": "75783e748e25214b",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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      "footprint": "viewers/footprint.html"
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        "seat": "z = 0",
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
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        "role": "eda",
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        "sha256": "42c9363a196e5f0928b8c5c70136c87f90b4ab98da6ee763b9d275d4d435df46",
        "checked": "2026-10-30",
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  }
}