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CY22381FXC
Public Made by Adomby adom
SPANSION Clock Generators / Frequency Synthesizers / PLL, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCY22381FXC
SPANSION · Clock Generators / Frequency Synthesizers / PLL · SOIC-8
CY22381FXC from SPANSION, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLKC | output | Configurable clock output C, taken from the crosspoint switch through a seven-bit post divider and designed to drive a single-point load of 15 pF total lumped capacitance. |
| 2 | GND | power_in | Ground reference for the device. |
| 3 | XTALIN | input | Reference crystal input or external reference clock input; the crystal range is 8 to 30 MHz and the external clock range is 1 to 166 MHz for commercial parts (1 to 150 MHz for industrial). |
| 4 | XTALOUT | output | Reference crystal feedback; it must be left floating when XTALIN is driven by an external reference clock. |
| 5 | CLKB | output | Configurable clock output B, taken from the crosspoint switch through a seven-bit post divider whose value is selected by FS, and designed to drive a single-point load of 15 pF total lumped capacitance. |
| 6 | CLKA | output | Configurable clock output A, taken from the crosspoint switch through a seven-bit post divider whose value is selected by FS, and designed to drive a single-point load of 15 pF total lumped capacitance. |
| 7 | VDD | power_in | Power supply, 3.135 V minimum, 3.3 V typical and 3.465 V maximum. |
| 8 | FS/SUSPEND/OE/SHUTDOWN | input | General-purpose CMOS input, programmable as frequency select, Suspend control, output enable (all outputs three-state when LOW), or full-chip shutdown (when LOW); its logic-high threshold is 70% of VDD minimum and its logic-low threshold is 30% of VDD maximum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SPANSION |
| Package | SOIC-8 |
| Category | Clock and Timing |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 3.135 | 3.3 | 3.465 | V | 5 | |
| Commercial operating temperature, ambient | TA | 0 | 70 | °C | Commercial | 5 | |
| Max. load capacitance | CLOAD_OUT | 15 | pF | 5 | |||
| External reference crystal | fREF | 8 | 30 | MHz | 5 | ||
| External reference clock, Commercial | fREF | 1 | 166 | MHz | External reference clock, commercial | 5 | |
| Power up time for all VDD's to reach minimum specified voltage | tPU | 0.05 | 500 | ms | Power ramps must be monotonic | 5 | |
| Output high current | IOH | 12 | 24 | mA | VOH = VDD, 0.5, VDD = 3.3 V | 5 | |
| Output low current | IOL | 12 | 24 | mA | VOL = 0.5 V, VDD = 3.3 V | 5 | |
| HIGH-level input voltage | VIH | 70 | VDD | CMOS levels, % of VDD | 5 | ||
| LOW-level input voltage | VIL | 30 | VDD | CMOS levels, % of VDD | 5 | ||
| Input HIGH current | IIH | 10 | µA | VIN = VDD, 0.3 V | 5 | ||
| Input LOW current | IIL | 10 | µA | VIN = +0.3 V | 5 | ||
| Output leakage current | IOZ | 10 | µA | Three-state outputs | 5 | ||
| Total power supply current in shutdown mode | IDDS | 5 | 20 | µA | Shutdown active | 5 | |
| Nominal crystal frequency | FNOM | 8 | 30 | MHz | Parallel resonance, fundamental mode | 6 | |
| Nominal load capacitance | CLNOM | 8 | 20 | pF | 6 | ||
| Equivalent series resistance (ESR) | R1 | 50 | Fundamental mode | 6 | |||
| Crystal drive level | DL | 0.5 | 2 | mW | No external series resistor assumed | 6 | |
| Output frequency | 1/t1 | 200 | MHz | Clock output limit, commercial | 7 | ||
| Output duty cycle | t2 | 45 | 50 | 55 | % | Duty cycle for outputs, defined as t2/t1, Fout < 100 MHz, divider >= 2, measured at VDD/2 | 7 |
| Output duty cycle | t2 | 40 | 50 | 60 | % | Duty cycle for outputs, defined as t2/t1, Fout > 100 MHz or divider = 1, measured at VDD/2 | 7 |
| Rising edge slew rate | t3 | 0.75 | 1.4 | V/ns | Output clock rise time, 20% to 80% of VDD | 7 | |
| Falling edge slew rate | t4 | 0.75 | 1.4 | V/ns | Output clock fall time, 20% to 80% of VDD | 7 | |
| Output three-state timing | t5 | 150 | 300 | ns | Time for output to enter or leave three-state mode after SHUTDOWN/OE switches | 7 | |
| Lock time | t7 | 1 | 3 | ms | PLL lock time from power up | 7 | |
| Supply voltage | -0.5 | 7 | V | 5 | |||
| DC input voltage | -0.5 | V | Printed as -0.5 V to + (VDD + 0.5 V) | 5 | |||
| Storage temperature | -65 | 125 | °C | 5 | |||
| Junction temperature | 125 | °C | 5 | ||||
| Package power dissipation | 250 | mW | 5 | ||||
| Static discharge voltage | 2000 | V | Per MIL-STD-883, Method 3015 | 5 | |||
| Latch up | -200 | 200 | mA | Per JEDEC 17 | 5 | ||
| Maximum programming cycles | 100 | 5 | |||||
| Commercial/industrial power-supply current, 3 outputs at 50 MHz (typical) | IDD | 35 | mA | 3.3 V power supply; 3 outputs at 50 MHz | 5 | ||
| Total power supply current, 3 outputs at 166 MHz (typical) | IDD | 70 | mA | 3.3 V power supply; 3 outputs at 166 MHz | 5 | ||
| Crystal load capacitance, minimum setting | CXTAL_MIN | 6 | pF | Capload at minimum setting | 5 | ||
| Crystal load capacitance, maximum setting | CXTAL_MAX | 30 | pF | Capload at maximum setting | 5 | ||
| Input pin capacitance | CIN | 7 | pF | Except crystal pins | 5 | ||
| Peak-to-peak period jitter | t6 | 200 | ps | CLK outputs measured at VDD/2 | 7 |
CAD (KiCad official)
- Symbol:
CY22381FXC - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
cy22381fxc-etched.step/cy22381fxc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cy22381fxc.step/cy22381fxc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SPANSION datasheet (14 pp, sha256
75783e748e25214b, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).