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CW32L052C8T6

CW · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

CW32L052C8T6 from CW, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Vcore	power_out	Internal regulator supply output that must be connected to ground through a 1 µF capacitor and is for internal circuit use only.
2	PC13	bidirectional	Standard TC I/O with reset-default function PC13; alternate functions RTC_1Hz, UART1_CTS, RTC_OUT, BTIM_ETR, GTIM3_ETR and RTC_TAMP are selected through GPIOC_AFRy.
3	PC14	bidirectional	Standard TC I/O with reset-default function PC14 that doubles as the OSC32_IN low-speed oscillator input; digital alternates AUTOTRIM_ETR, GTIM1_CH4, UART1_RTS, UART1_TXD, SPI2_MISO, GTIM3_TOGP and GTIM3_CH1 are selected through GPIOC_AFRy.
4	PC15	bidirectional	Standard TC I/O with reset-default function PC15 that doubles as the OSC32_OUT low-speed oscillator output; digital alternates HSE_OUT, GTIM1_CH3, GTIM1_ETR, UART1_RXD, SPI2_MOSI, GTIM3_TOGN and GTIM3_CH2 are selected through GPIOC_AFRy.
5	PF00	bidirectional	Standard TC I/O with reset-default function PF00 that doubles as the OSC_IN high-speed oscillator input; digital alternates AUTOTRIM_ETR, GTIM1_CH2, I2C1_SDA, BTIM1_TOGN, SPI2_SCK, GTIM2_TOGP and GTIM3_CH3 are selected through GPIOF_AFRy.
6	PF01	bidirectional	Standard TC I/O with reset-default function PF01 that doubles as the OSC_OUT high-speed oscillator output; digital alternates LSE_OUT, GTIM1_CH1, I2C1_SCL, BTIM1_TOGP, SPI2_CS, GTIM2_TOGN and GTIM3_CH4 are selected through GPIOF_AFRy.
7	NRST	input	Chip reset input with internal pull-up of 7-9 kΩ; the reset pulse must be at least 20 µs and the input low level must be below 0.3VDD.
8	VSSA	power_in	Analog ground.
9	VDDA	power_in	Analog supply for the ADC, reset circuit and internal RC oscillator, 1.65 V to 5.5 V, which must always be greater than or equal to VDD.
10	PA00	bidirectional	TTa I/O with analog functions ADC_AIN0, VC1_CH0 and LVD_CH1 set by peripheral registers; digital alternates UART3_CTS, UART2_CTS, RTC_TAMP, VC1_OUT, SPI2_MISO, GTIM2_CH1 and GTIM2_ETR are selected through GPIOA_AFRy.
11	PA01	bidirectional	TTa I/O with analog functions ADC_AIN1, VC1_CH1 and SEG19 set by peripheral registers; digital alternates UART3_RTS, UART2_RTS, I2C2_SCL, LVD_OUT, SPI2_MOSI, GTIM2_CH2 and RTC_TAMP are selected through GPIOA_AFRy.
12	PA02	bidirectional	TTa I/O with analog functions ADC_AIN2, VC1_CH2 and SEG18 set by peripheral registers; digital alternates UART3_TXD, UART2_TXD, I2C2_SDA, VC2_OUT, SPI2_SCK, GTIM2_CH3 and AUTOTRIM_ETR are selected through GPIOA_AFRy.
13	PA03	bidirectional	TTa I/O with analog functions ADC_AIN3, VC1_CH3 and SEG17 set by peripheral registers; digital alternates UART3_RXD, UART2_RXD, GTIM2_CH2, PCLK_OUT, SPI2_CS, GTIM2_CH4 and ATIM_CH3A are selected through GPIOA_AFRy.
14	PA04	bidirectional	TTa I/O with analog functions ADC_AIN4 and VC1_CH4 set by peripheral registers; digital alternates UART1_TXD, UART2_CTS, I2C2_SCL, HCLK_OUT, SPI1_CS, GTIM2_ETR and ATIM_CH2A are selected through GPIOA_AFRy.
15	PA05	bidirectional	TTa I/O with analog functions ADC_AIN5 and VC1_CH5 set by peripheral registers; digital alternates GTIM2_ETR, UART2_RTS, I2C2_SDA, BTIM2_TOGN, SPI1_SCK, GTIM2_CH1 and ATIM_CH1A are selected through GPIOA_AFRy.
16	PA06	bidirectional	TTa I/O with analog functions ADC_AIN6, VC1_CH6 and SEG16 set by peripheral registers; digital alternates GTIM3_CH1, UART2_TXD, VC1_OUT, BTIM2_TOGP, SPI1_MISO, GTIM1_CH1 and ATIM_BK are selected through GPIOA_AFRy.
17	PA07	bidirectional	TTa I/O with analog functions ADC_AIN7, VC1_CH7 and SEG15 set by peripheral registers; digital alternates GTIM2_CH1, UART2_RXD, VC2_OUT, BTIM1_TOGN, SPI1_MOSI, GTIM1_CH2 and ATIM_CH1B are selected through GPIOA_AFRy.
18	PB00	bidirectional	TTa I/O with analog functions ADC_AIN10/ExRef, VC2_CH0, LVD_CH2 and SEG12 set by peripheral registers; digital alternates UART2_RXD, UART1_CTS, I2C2_SCL, BTIM1_TOGP, HSIOSC_OUT, GTIM1_CH3 and ATIM_CH2B are selected through GPIOB_AFRy.
19	PB01	bidirectional	TTa I/O with analog functions ADC_AIN11, VC2_CH1 and SEG11 set by peripheral registers; digital alternates UART2_TXD, UART1_RTS, I2C2_SDA, GTIM2_TOGP, BTIM3_TOGN, GTIM1_CH4 and ATIM_CH3B are selected through GPIOB_AFRy.
20	PB02	bidirectional	TTa I/O with analog functions ADC_AIN12 and VC2_CH2 set by peripheral registers; digital alternates UART2_CTS, UART1_TXD, LPTIM_OUT, GTIM2_TOGN, BTIM3_TOGP, GTIM1_ETR and ATIM_CH1A are selected through GPIOB_AFRy.
21	PB10	bidirectional	TTa I/O with analog functions VC2_CH3 and SEG10 set by peripheral registers; digital alternates UART2_RTS, UART1_RXD, I2C1_SCL, I2C2_SCL, SPI2_SCK, GTIM2_CH3 and ATIM_CH2A are selected through GPIOB_AFRy.
22	PB11	bidirectional	TTa I/O with analog functions LVD_CH3 and SEG9 set by peripheral registers; digital alternates GTIM3_ETR, UART1_TXD, I2C1_SDA, I2C2_SDA, BTIM_ETR, GTIM2_CH4 and ATIM_CH3A are selected through GPIOB_AFRy.
23	VSS	power_in	Digital ground.
24	VDD	power_in	Digital supply for the I/O ports and internal regulator, 1.65 V to 5.5 V; all VDD pins must be powered at the same voltage.
25	PB12	bidirectional	TTa I/O with analog function SEG8 set by peripheral registers; digital alternates GTIM2_TOGP, GTIM3_CH4, LSE_OUT, SPI2_CS, SPI1_CS, GTIM1_TOGP and ATIM_BK are selected through GPIOB_AFRy.
26	PB13	bidirectional	TTa I/O with analog function SEG7 set by peripheral registers; digital alternates GTIM2_TOGN, GTIM3_CH3, I2C2_SCL, SPI2_SCK, SPI1_SCK, GTIM1_TOGN and ATIM_CH1B are selected through GPIOB_AFRy.
27	PB14	bidirectional	TTa I/O with analog function SEG6 set by peripheral registers; digital alternates GTIM2_CH1, GTIM3_CH2, I2C2_SDA, SPI2_MISO, SPI1_MISO, RTC_OUT and ATIM_CH2B are selected through GPIOB_AFRy.
28	PB15	bidirectional	TTa I/O with analog function SEG5 set by peripheral registers; digital alternates GTIM2_CH2, GTIM3_CH1, BTIM2_TOGN, SPI2_MOSI, SPI1_MOSI, RTC_1Hz and ATIM_CH3B are selected through GPIOB_AFRy.
29	PA08	bidirectional	TTa I/O with analog functions VC2_CH4 and SEG0 set by peripheral registers; digital alternates LPTIM_ETR, UART1_TXD, BTIM2_TOGP, MCO_OUT, LVD_OUT, GTIM3_ETR and ATIM_CH1A are selected through GPIOA_AFRy.
30	PA09	bidirectional	TTa I/O with analog functions VC2_CH5 and COM0 set by peripheral registers; digital alternates UART3_TXD, UART1_RXD, I2C1_SCL, BTIM1_TOGN, SPI1_CS, GTIM3_CH1 and ATIM_CH2A are selected through GPIOA_AFRy.
31	PA10	bidirectional	TTa I/O with analog functions VC2_CH6 and COM1 set by peripheral registers; digital alternates UART3_RXD, UART1_CTS, I2C1_SDA, BTIM1_TOGP, SPI1_SCK, GTIM3_CH2 and ATIM_CH3A are selected through GPIOA_AFRy.
32	PA11	bidirectional	TTa I/O with analog functions VC2_CH7 and COM2 set by peripheral registers; digital alternates UART3_CTS, UART1_RTS, I2C2_SCL, VC1_OUT, SPI1_MISO and GTIM3_CH3 are selected through GPIOA_AFRy.
33	PA12	bidirectional	TTa I/O with analog function COM3 set by peripheral registers; digital alternates UART3_RTS, BTIM_ETR, I2C2_SDA, VC2_OUT, SPI1_MOSI, GTIM3_CH4 and ATIM_ETR are selected through GPIOA_AFRy.
34	PA13/SWDIO	bidirectional	Standard TC I/O that is configured as the SWDIO debug pin after reset with its internal pull-up enabled by default; alternates I2C1_SDA, UART1_RXD, UART2_TXD, I2C2_SCL and IR_OUT are selected through GPIOA_AFRy.
35	PF06	bidirectional	Standard TC I/O with digital alternates UART3_CTS, I2C1_SCL, GTIM1_TOGP, UART2_CTS, I2C2_SCL, GTIM3_TOGP and BTIM3_TOGN selected through GPIOF_AFRy.
36	PF07	bidirectional	Standard TC I/O with digital alternates UART3_RTS, I2C1_SDA, GTIM1_TOGN, UART2_RTS, I2C2_SDA, GTIM3_TOGN and BTIM3_TOGP selected through GPIOF_AFRy.
37	PA14/SWCLK	bidirectional	Standard TC I/O that is configured as the SWCLK debug pin after reset with its internal pull-up enabled by default; alternates UART3_TXD, I2C1_SCL, UART1_TXD, UART2_RXD and I2C2_SDA are selected through GPIOA_AFRy.
38	PA15	bidirectional	TTa I/O with analog function SEG55 set by peripheral registers; digital alternates UART3_RXD, GTIM2_CH1, UART1_RXD, UART2_TXD, SPI1_CS, GTIM2_ETR and ATIM_CH1B are selected through GPIOA_AFRy.
39	PB03	bidirectional	TTa I/O with analog functions SEG27 and VLCD4 set by peripheral registers; digital alternates UART3_RTS, GTIM2_CH2, UART1_CTS, UART2_TXD, SPI1_SCK, GTIM1_ETR and ATIM_CH2B are selected through GPIOB_AFRy.
40	PB04	bidirectional	TTa I/O with analog functions SEG26 and VLCD3 set by peripheral registers; digital alternates UART3_CTS, GTIM2_ETR, UART1_RTS, UART2_RXD, SPI1_MISO, GTIM1_CH1 and ATIM_CH3B are selected through GPIOB_AFRy.
41	PB05	bidirectional	TTa I/O with analog functions SEG25 and VLCD2 set by peripheral registers; digital alternates UART1_RXD, GTIM3_CH4, LPTIM_CH1, UART2_RTS, SPI1_MOSI, GTIM1_CH2 and ATIM_CH1A are selected through GPIOB_AFRy.
42	PB06	bidirectional	TTa I/O with analog functions SEG24 and VLCD1 set by peripheral registers; digital alternates UART3_TXD, GTIM3_CH3, LPTIM_ETR, I2C1_SCL, SPI2_MOSI, GTIM1_TOGP and ATIM_CH2A are selected through GPIOB_AFRy.
43	PB07	bidirectional	TTa I/O with digital alternates UART3_RXD, GTIM3_CH2, LPTIM_CH2, I2C1_SDA, SPI2_MISO, GTIM1_TOGN and ATIM_CH3A selected through GPIOB_AFRy.
44	PF03/BOOT	input	Dedicated BOOT pin that selects at startup between running the internal Bootloader and running the user program.
45	PB08	bidirectional	TTa I/O with analog function SEG53 set by peripheral registers; digital alternates I2C1_SCL, GTIM3_CH1, UART2_TXD, GTIM2_CH2, SPI2_SCK, GTIM1_CH3 and ATIM_ETR are selected through GPIOB_AFRy.
46	PB09	bidirectional	TTa I/O with analog function SEG52 set by peripheral registers; digital alternates I2C1_SDA, GTIM2_CH1, UART2_RXD, IR_OUT, SPI2_CS, GTIM1_CH4 and ATIM_BK are selected through GPIOB_AFRy.
47	VSS	power_in	Digital ground.
48	VDD	power_in	Digital supply for the I/O ports and internal regulator, 1.65 V to 5.5 V; all VDD pins must be powered at the same voltage.

Key specifications

Parameter	Value
Manufacturer	CW
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
External main supply voltage (VDD - VSS)	VDD - VSS	-0.3		6	V		41
External analog supply voltage (VDDA - VSS)	VDDA-VSS	-0.3		6	V		41
Maximum allowed difference VDD above VDDA	VDD-VDDA			0.3	V		41
Voltage difference between VDD pins	ΔVDDx			0.05	V		41
Voltage difference between VSS pins	/VSSX-VSS/			0.05	V		41
Total current sunk by all VDD supply lines	ΣIVDD			120	mA		41
Total current sourced by all VSS supply lines	ΣIVSS			-120	mA		41
Current sunk by a single VDD supply line	IVDD(PIN)			100	mA		41
Current sourced by a single VSS supply line	IVSS(PIN)			-100	mA		41
Current sunk by a single I/O or control pin	IIO(PIN)			25	mA		41
Current sourced by a single I/O or control pin	IIO(PIN)			-25	mA		41
Total current sunk by all I/O and control pins	ΣIIO(PIN)			80	mA		41
Total current sourced by all I/O and control pins	ΣIIO(PIN)			-80	mA		41
Injection current, TC and RST pins	IINJ(PIN)	-5		5	mA	TC and RST pins	41
Injection current, TTa pins	IINJ(PIN)	-5		5	mA	TTa pins	41
Total injection current, all I/O and control pins	ΣIINJ(PIN)	-25		25	mA		41
Storage temperature range	TSTG	-65		150	℃		42
Maximum junction temperature	TJ			105	℃		42
ESD voltage, human body model	VESD(HBM)			8	kV	TA = +25℃, JESD22-A115C	53
ESD voltage, charged device model	VESD(CDM)			2	kV	TA = +25℃, JESD22-A115C	53
Internal AHB bus frequency	fHCLK	0		48	MHz	VDD≥ 1.8V	43
Internal APB bus frequency	fPCLK	0		48	MHz	VDD≥ 1.8V	43
Internal AHB bus frequency	fHCLK	0		24	MHz	1.65V ≤ VDD ＜ 1.8V	43
Internal APB bus frequency	fPCLK	0		24	MHz	1.65V ≤ VDD ＜ 1.8V	43
Standard operating voltage	VDD	1.65		5.5	V		43
Analog operating voltage	VDDA	1.65		5.5	V	须等于 VDD	43
I/O input voltage (TC I/O)	VIN	-0.3			V	TC I/O	43
I/O input voltage (TTa I/O)	VIN	-0.3			V	TTa I/O	43
Power dissipation, LQFP48	PD			364	mW	温度标号 6：TA=85℃	43
Ambient temperature, maximum power dissipation	TA	-40		85	℃	最大功率耗散 (temperature code 6)	43
Ambient temperature, low power dissipation	TA	-40		105	℃	低功率耗散 (see note 2)	43
Junction temperature range	TJ	-40		105	℃	温度标号 6	43
Power-on/power-down reset threshold	VPOR/BOR	1.45	1.5	1.55	V	下降沿 (falling edge)	44
Power-on/power-down reset threshold	VPOR/BOR	1.5	1.55	1.6	V	上升沿 (rising edge)	44
Reset duration	tRSTTEMPO	4	6.5	13	ms		44
Internal 1.5V reference voltage	VREFINT1V5	1.485	1.5	1.515	V	-40℃ < TA < +85℃	44
Internal 2.5V reference voltage	VREFINT2V5	2.475	2.5	2.525	V	-40℃ < TA < +85℃	44
Internal reference voltage distribution over full temperature range	ΔVREFINT			10	mV	VDDA = 3V	44
Internal reference voltage temperature coefficient	TCoeff	-60		60	ppm/℃		44
Run-mode supply current, code from FLASH, 48MHz	IDD		8.2	8.6	mA	VDD=VDDA=5.5V; HSI or HSE clock; all peripherals on; code from FLASH; max at TA=85℃	45
Run-mode supply current, code from RAM, 48MHz	IDD		6.4	6.7	mA	VDD=VDDA=5.5V; HSI or HSE clock; all peripherals on; code from RAM; max at TA=85℃	45
Sleep-mode supply current, 48MHz	IDD		4.6	4.9	mA	VDD=VDDA=5.5V; HSI or HSE clock; all peripherals on; code from FLASH or RAM; max at TA=85℃	45
DeepSleep supply current, all oscillators off	IDD		0.5	7	μA	Regulator in run mode; typ at VDD=VDDA=3.3V; max at TA=85℃	46
DeepSleep supply current, LSI and IWDT on	IDD		1.4	8	μA	Regulator in run mode; typ at VDD=VDDA=3.3V; max at TA=85℃	46
DeepSleep supply current, LSE on	IDD		0.9	7.8	μA	Regulator in run mode; typ at VDD=VDDA=3.3V; max at TA=85℃	46
HSI factory calibration accuracy	ACCHSI	-2		2	%	TA = -40℃ ~ +85℃	51
User external clock source frequency (HSE)	fHSE_EXT	1		32	MHz		48
HSE oscillator frequency (crystal/ceramic resonator)	fOSC_IN	4	8	32	MHz		50
FLASH supply current, write mode	IDD			3.5	mA	写模式	52
FLASH supply current, erase mode	IDD			2	mA	擦除模式	52
FLASH programming voltage	Vprog	1.65		5.5	V		52
FLASH endurance	NNED	20000			次	TA = -40℃ ~ +85℃	52
FLASH data retention	tRET	25			年	TA = 85℃	52
High-level output voltage	VOH	3.02			V	Sourcing 10mA, VDD = 3.3V	55
Low-level output voltage	VOL			0.23	V	Sinking 10mA, VDD = 3.3V	55
I/O input leakage current, digital mode	Iikg	-0.1		0.1	μA	TC and TTa I/O, digital mode, VSS ≤ VIN ≤ VDDIOx	54
Weak pull-up equivalent resistance	RPU	50	80	180	kΩ	VIN = VSS	54
ADC supply voltage when ADC is enabled	VDDA	1.65		5.5	V		58
ADC total unadjusted error	ET	-3	2.5	3	LSB	fADC = 24MHz, VDDA = 1.65V ~ 5.5V, TA = -40℃ ~+85℃	59
HSI factory calibration accuracy	ACCHSI	-0.5		0.5	%	TA = +25℃	51

CAD (KiCad official)

Symbol: CW32L052C8T6
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: cw32l052c8t6-etched.step / cw32l052c8t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cw32l052c8t6.step / cw32l052c8t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: CW datasheet (79 pp, sha256 eed9d435f5af5b43, retrieved 2026-10-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF