# CSD16301Q2

**Texas Instruments** · MOSFETs · WSON-6(2x2)

CSD16301Q2 from Texas Instruments, in a WSON-6(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D | output | Drain connection for the 25V N-channel power MOSFET; rated maximum drain-to-source voltage VDS=25V with RDS(on)=19mΩ at VGS=8V. |
| 2 | D | output | Drain connection; multiple drain pins internally connected for thermal management to achieve junction-to-case thermal resistance RθJC=8.4°C/W. |
| 3 | D | output | Drain connection; part of multi-pin drain configuration for minimizing thermal resistance and distributing current. |
| 4 | D | output | Drain connection; internally connected to other drain pins for low on-state resistance of 19mΩ to 27mΩ depending on gate drive. |
| 5 | D | output | Drain connection; supports continuous drain current up to 5A (package limited) with all drain pins interconnected for thermal dissipation. |
| 6 | G | input | Gate control terminal for N-channel MOSFET switching; gate-to-source voltage absolute maximum -8V to +10V, gate-to-source threshold voltage VGS(th)=1.1V typical, total gate charge Qg=2nC at VDS=10V, gate-to-drain charge Qgd=0.4nC. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6(2x2) |
| Category | Transistors/Thyristors |
| Pins | 7 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-to-source voltage (BVDSS) | BVDSS | 25 |  |  | V | VGS = 0V, ID = 250μA | 3 |
| Drain-to-source leakage current | IDSS |  |  | 1 | μA | VGS = 0V, VDS = 20V | 3 |
| Gate-to-source leakage current | IGSS |  |  | 100 | nA | VDS = 0V, VGS = +10/–8V | 3 |
| Gate-to-source threshold voltage | VGS(th) | 0.9 | 1.1 | 1.55 | V | VDS = VGS, IDS = 250μA | 3 |
| Drain-to-source on resistance | RDS(on) |  | 27 | 34 | mΩ | VGS = 3V, IDS = 4A | 3 |
| Drain-to-source on resistance | RDS(on) |  | 23 | 29 | mΩ | VGS = 4.5V, IDS = 4A | 3 |
| Drain-to-source on resistance | RDS(on) |  | 19 | 24 | mΩ | VGS = 8V, IDS = 4A | 3 |
| Input capacitance | CISS |  | 260 | 340 | pF | VGS = 0V, VDS = 12.5V, ƒ = 1MHz | 3 |
| Output capacitance | COSS |  | 165 | 215 | pF | VGS = 0V, VDS = 12.5V, ƒ = 1MHz | 3 |
| Reverse transfer capacitance | CRSS |  | 13 | 17 | pF | VGS = 0V, VDS = 12.5V, ƒ = 1MHz | 3 |
| Series gate resistance | Rg |  | 1.3 | 2.6 | Ω |  | 3 |
| Gate charge total (4.5 V) | Qg |  | 2 | 2.8 | nC | VDS = 10V, IDS = 4A | 3 |
| Diode forward voltage | VSD |  | 0.8 | 1 | V | IDS = 4A, VGS = 0V | 3 |
| Junction-to-ambient thermal resistance | RθJA |  |  | 65 | °C/W | TA = 25°C (unless otherwise stated); device on 1in² 2oz Cu pad (Max RθJA = 65°C/W) | 3 |
| Junction-to-case thermal resistance | RθJC |  |  | 8.4 | °C/W | TA = 25°C (unless otherwise stated) | 3 |
| Drain-to-source voltage | VDS |  |  | 25 | V | TA = 25°C | 1 |
| Gate-to-source voltage | VGS | -8 |  | 10 | V | TA = 25°C | 1 |
| Continuous Drain Current (Package Limited) | ID |  |  | 5 | A | TA = 25°C | 1 |
| Continuous Drain Current (Silicon Limited), TC = 25°C | ID |  |  | 20 | A | TC = 25°C | 1 |
| Continuous Drain Current | ID |  |  | 8.2 | A | TA = 25°C; footnote 1 (RθJA on 1in² pad) | 1 |
| Pulsed Drain Current | IDM |  |  | 85 | A | pulse duration ≤ 100μs, duty cycle ≤ 1% | 1 |
| Power Dissipation | PD |  |  | 2.5 | W | TA = 25°C; footnote 1 (RθJA on 1in² pad) | 1 |
| Power Dissipation, TC = 25°C | PD |  |  | 15 | W | TC = 25°C | 1 |
| Operating junction and storage temperature | TJ, TSTG | -55 |  | 150 | °C |  | 1 |
| Avalanche energy, single pulse | EAS |  |  | 10 | mJ | ID = 14A, L = 0.1mH, RG = 25Ω | 1 |
| Forward transconductance | gfs |  | 16.5 |  | S | VDS = 15V, IDS = 4A | 3 |
| Gate charge gate-to-drain | Qgd |  | 0.4 |  | nC |  | 3 |
| Gate charge gate-to-source | Qgs |  | 0.6 |  | nC |  | 3 |
| Gate charge at Vth | Qg(th) |  | 0.3 |  | nC |  | 3 |
| Output charge | QOSS |  | 3 |  | nC | VDS = 12.5V, VGS = 0V | 3 |
| Turnon delay time | td(on) |  | 2.7 |  | ns | VDS = 12.5V, VGS = 4.5V, IDS = 4A, RG = 2Ω | 3 |
| Rise time | tr |  | 4.4 |  | ns | VDS = 12.5V, VGS = 4.5V, IDS = 4A, RG = 2Ω | 3 |
| Turnoff delay time | td(off) |  | 4.1 |  | ns | VDS = 12.5V, VGS = 4.5V, IDS = 4A, RG = 2Ω | 3 |
| Fall time | tf |  | 1.7 |  | ns | VDS = 12.5V, VGS = 4.5V, IDS = 4A, RG = 2Ω | 3 |
| Reverse recovery charge | Qrr |  | 5.1 |  | nC | VDD = 12.5V, IF = 4A, di/dt = 200A/μs | 3 |
| Reverse recovery time | trr |  | 11 |  | ns | VDD = 12.5V, IF = 4A, di/dt = 200A/μs | 3 |

## CAD (KiCad official)

- Symbol: `CSD16301Q2`
- Footprint: `Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm`
- 3D model: WSON-6(2x2) (KiCad packages3D, STEP)
- 3D model files: `csd16301q2-etched.step` / `csd16301q2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `csd16301q2.step` / `csd16301q2.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/csd16301q2.pdf) (16 pp, sha256 `e81fd6c7ebe1f521`, retrieved 2026-09-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/csd16301q2-datasheet.pdf)