CS8416-CSZR

{
  "slug": "cs8416-cszr",
  "version": "0.1.2",
  "type": "component",
  "description": "Cirrus Logic Audio Interface ICs, SOIC-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "communication interface chip",
    "cs8416-cszr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cs8416-cszr.kicad_sym",
    "cs8416-cszr.kicad_mod",
    "cs8416-cszr.glb",
    "cs8416-cszr.step",
    "cs8416-cszr.lbr",
    "docs/hero.png",
    "docs/cs8416-cszr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cs8416-cszr-hero.glb",
    "cs8416-cszr-hero.overlay.json"
  ],
  "component": {
    "mpn": "CS8416-CSZR",
    "manufacturer": "Cirrus Logic",
    "package": "SOIC-28",
    "pin_count": 28,
    "category": "Communication Interface Chip",
    "subcategory": "Audio Interface ICs",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/8f2da87ad1926efe8d911b810a837856.pdf",
    "parts": {
      "symbol": "cs8416-cszr.kicad_sym",
      "footprint": "cs8416-cszr.kicad_mod",
      "model_3d": "cs8416-cszr-hero.glb",
      "model_3d_plain": "cs8416-cszr.glb",
      "model_3d_step": "cs8416-cszr-etched.step",
      "model_3d_step_plain": "cs8416-cszr.step",
      "lbr": "cs8416-cszr.lbr"
    },
    "distributor_links": {
      "lcsc": "C17499513",
      "digikey": "598-CS8416-CSZRTR-ND",
      "mouser": "777-CS8416-CSZR"
    },
    "distributor_check": {
      "checked_at": "2026-11-13T00:08:23Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "598-CS8416-CSZRTR-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "777-CS8416-CSZR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "RXP3",
        "type": "input",
        "description": "Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND."
      },
      {
        "number": "2",
        "name": "RXP2",
        "type": "input",
        "description": "Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND."
      },
      {
        "number": "3",
        "name": "RXP1",
        "type": "input",
        "description": "Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND."
      },
      {
        "number": "4",
        "name": "RXP0",
        "type": "input",
        "description": "Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND."
      },
      {
        "number": "5",
        "name": "RXN",
        "type": "input",
        "description": "Negative AES3/SPDIF input forming a differential pair with RXP[7:0]; in single-ended operation it is AC-coupled to ground through a capacitor."
      },
      {
        "number": "6",
        "name": "VA",
        "type": "power_in",
        "description": "Analog power supply, nominally +3.3 V (VA range 3.13 V to 3.46 V); noise on this pin directly affects recovered-clock jitter."
      },
      {
        "number": "7",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground for the analog circuitry; AGND and DGND should be connected to a common ground area under the chip."
      },
      {
        "number": "8",
        "name": "FILT",
        "type": "output",
        "description": "PLL loop filter output; an RC network must be connected between this pin and analog ground, with the ground end returned directly to AGND for minimum jitter."
      },
      {
        "number": "9",
        "name": "RST",
        "type": "input",
        "description": "Reset input; when low the CS8416 enters a low-power mode with all internal states reset, and RST must be held low until supplies and input clocks are stable at power-up."
      },
      {
        "number": "10",
        "name": "RXP4",
        "type": "input",
        "description": "Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND."
      },
      {
        "number": "11",
        "name": "RXP5",
        "type": "input",
        "description": "Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND."
      },
      {
        "number": "12",
        "name": "RXP6",
        "type": "input",
        "description": "Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND."
      },
      {
        "number": "13",
        "name": "RXP7",
        "type": "input",
        "description": "Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND."
      },
      {
        "number": "14",
        "name": "AD0 / CS",
        "type": "input",
        "description": "Address bit 0 in I2C mode or control port chip select in SPI mode; a falling edge selects SPI mode, and with no falling edge the device defaults to I2C mode."
      },
      {
        "number": "15",
        "name": "AD1 / CDIN",
        "type": "input",
        "description": "Address bit 1 in I2C mode or serial control data input in SPI mode."
      },
      {
        "number": "16",
        "name": "SCL / CCLK",
        "type": "input",
        "description": "Control port clock (I2C SCL or SPI CCLK), used to clock control data in and out; it is an open-drain output requiring an external pull-up resistor to VL."
      },
      {
        "number": "17",
        "name": "SDA / CDOUT",
        "type": "bidirectional",
        "description": "Serial control data I/O in I2C mode (open drain, requires external pull-up to VL) or control data output in SPI mode."
      },
      {
        "number": "18",
        "name": "AD2 / GPO2",
        "type": "output",
        "description": "General purpose output 2; when using I2C control port this pin must be pulled high or low through a 47 kOhm resistor to set the AD2 address bit."
      },
      {
        "number": "19",
        "name": "GPO1",
        "type": "output",
        "description": "General purpose output 1, source selected through GPO1SEL bits; all GPO pins default to GND after reset."
      },
      {
        "number": "20",
        "name": "GPO0",
        "type": "output",
        "description": "General purpose output 0, source selected through GPO0SEL bits; all GPO pins default to GND after reset."
      },
      {
        "number": "21",
        "name": "VL",
        "type": "power_in",
        "description": "Logic power supply setting the I/O and receiver input levels, nominally +3.3 V or +5.0 V (3.13 V to 5.25 V range)."
      },
      {
        "number": "22",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital and I/O ground for the I/O and core logic; AGND and DGND should be connected to a common ground area under the chip."
      },
      {
        "number": "23",
        "name": "VD",
        "type": "power_in",
        "description": "Digital core power supply, nominally +3.3 V (3.13 V to 3.46 V range)."
      },
      {
        "number": "24",
        "name": "RMCK",
        "type": "output",
        "description": "Input section recovered master clock output, 256x Fs by default or 128x Fs when RMCKF is set; may be placed in high impedance by the RXD bit."
      },
      {
        "number": "25",
        "name": "OMCK",
        "type": "input",
        "description": "System clock input; when OMCK System Clock Mode is enabled it is output on RMCK upon PLL unlock and serves as the OMCK/RMCK ratio reference."
      },
      {
        "number": "26",
        "name": "SDOUT",
        "type": "output",
        "description": "Serial audio output data; in Software Mode this pin must be pulled high to VL through a 47 kOhm resistor to select Software Mode."
      },
      {
        "number": "27",
        "name": "OSCLK",
        "type": "bidirectional",
        "description": "Serial audio output bit clock, an output in master mode and an input in slave mode, for data on SDOUT."
      },
      {
        "number": "28",
        "name": "OLRCK",
        "type": "bidirectional",
        "description": "Serial audio output left/right word clock, an output at the sample rate Fs in master mode and an input in slave mode."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Mode ambiguity: this pinout is the Software Mode table (datasheet section 2.1). In Hardware Mode (se; No separate SOIC pin table: the datasheet's pin tables are labelled TSSOP (section 2.1/3.1), and its; Pin types are inferred from datasheet wording: FILT is listed as 'Output' and RMCK/SDOUT/GPO pins as"
        ],
        "pages_sent": 60,
        "cost_usd": 0.2775,
        "at": "2026-11-13T00:08:08"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/8f2da87ad1926efe8d911b810a837856.pdf",
        "pages": 60,
        "sha256": "85bb158d11c6e9bf",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 28,
        "described": 28,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cs8416-cszr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          10.3,
          17.9,
          2.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "b889a13dbe9ec59e79fa9f1b5118b00bfa54f9582392335ff3365b64afc264b1",
        "checked": "2026-11-13",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cs8416-cszr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          10.3,
          17.9,
          2.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "9090d1539f1505a39f7984b13ef8c54e5c477cd71a9b026a25c91b1c4bd6f0be",
        "checked": "2026-11-13",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ],
    "package_dims": {
      "package_code": "28L SOIC (300 MIL BODY)",
      "source_page": 56,
      "D": {
        "nom_mm": 17.9,
        "range_mm": [
          17.7,
          18.1
        ]
      },
      "E1": {
        "nom_mm": 7.5,
        "range_mm": [
          7.4,
          7.6
        ]
      },
      "E": {
        "nom_mm": 10.34,
        "range_mm": [
          10.0,
          10.65
        ]
      },
      "e": {
        "nom_mm": 1.27,
        "range_mm": [
          1.02,
          1.52
        ]
      },
      "A": {
        "nom_mm": 2.5,
        "range_mm": [
          2.35,
          2.65
        ]
      },
      "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
      "model_check": {
        "file": "cs8416-cszr.step",
        "verdict": "PASS",
        "reasons": [
          "height and body within the datasheet's package drawing"
        ],
        "by": "factory/package_fit.py"
      }
    }
  }
}