component

CS8416-CSZR

Public Made by Adom

by adom

Cirrus Logic Audio Interface ICs, SOIC-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chipcs8416-cszrfactory-2.0.0extractor-text

Verified CS8416-CSZR

by Ray · last 13 Nov 2026 · 3 records · files match
SymbolFootprint3D modelPins

Verification log 3 records

13 Nov 2026RayRebuilt by the parts factory: tier lcsc, 28 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CS8416-CSZR · SOIC-28 · 28 pins
  • ✓copper: 28 copper pads, none touching another net
  • ✓datasheet: all 28 pin names found in the 60-page datasheet
  • ✓distributor: lcsc C17499513, digikey 598-CS8416-CSZRTR-ND, mouser 777-CS8416-CSZR
  • ✓family: SOIC-28W_7.5x17.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-cednmujn/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.56)
  • ✓pads: 28 pins = 28 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 28 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 46 kB, viewers/symbol.html 21 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cs8416-cszr.kicad_sym✓ cs8416-cszr.kicad_mod✓ cs8416-cszr.step
12 Nov 2026RayRebuilt by the parts factory: tier lcsc, 28 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CS8416-CSZR · SOIC-28 · 28 pins
  • ✓copper: 28 copper pads, none touching another net
  • ✓datasheet: all 28 pin names found in the 60-page datasheet
  • ✓distributor: lcsc C17499513, digikey 598-CS8416-CSZRTR-ND, mouser 777-CS8416-CSZR
  • ✓family: SOIC-28W_7.5x17.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-n8hyd0dw/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.56)
  • ✓pads: 28 pins = 28 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 28 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 46 kB, viewers/symbol.html 21 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cs8416-cszr.kicad_sym✓ cs8416-cszr.kicad_mod✓ cs8416-cszr.step
12 Nov 2026RayPublished by the parts factory: tier lcsc, 28 pinsre-verified
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CS8416-CSZR · SOIC-28 · 28 pins
  • ✓copper: 28 copper pads, none touching another net
  • ✓datasheet: all 28 pin names found in the 60-page datasheet
  • ✓distributor: lcsc C17499513, digikey 598-CS8416-CSZRTR-ND, mouser 777-CS8416-CSZR
  • ✓family: SOIC-28W_7.5x17.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-w7bei035/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.56)
  • ✓pads: 28 pins = 28 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 28 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 46 kB, viewers/symbol.html 21 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files! cs8416-cszr.kicad_sym✓ cs8416-cszr.kicad_mod✓ cs8416-cszr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cs8416-cszr: viewers · Ray
cs8416-cszr-etched.glb Publish 0.1.0 · Ray
cs8416-cszr-etched.step cs8416-cszr: factory component page (tier=lcsc) · Ray
cs8416-cszr-hero.glb cs8416-cszr: hero GLB from the etched model (keeps the MPN mark) · Ray
cs8416-cszr-hero.overlay.json cs8416-cszr: hero GLB from the etched model (keeps the MPN mark) · Ray
cs8416-cszr.glb Publish 0.1.0 · Ray
cs8416-cszr.kicad_mod Publish 0.1.0 · Ray
cs8416-cszr.kicad_sym Publish 0.1.1 · Ray
cs8416-cszr.lbr Publish 0.1.1 · Ray
cs8416-cszr.step Publish 0.1.0 · Ray
package.json Publish 0.1.2 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.2 · Ray
verification.json Verified: Rebuilt by the parts factory: tier lcsc, 28 pins · Ray

CS8416-CSZR

Cirrus Logic · Audio Interface ICs · SOIC-28

CS8416-CSZR from Cirrus Logic, in a SOIC-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RXP3 input Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND.
2 RXP2 input Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND.
3 RXP1 input Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND.
4 RXP0 input Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND.
5 RXN input Negative AES3/SPDIF input forming a differential pair with RXP[7:0]; in single-ended operation it is AC-coupled to ground through a capacitor.
6 VA power_in Analog power supply, nominally +3.3 V (VA range 3.13 V to 3.46 V); noise on this pin directly affects recovered-clock jitter.
7 AGND power_in Analog ground for the analog circuitry; AGND and DGND should be connected to a common ground area under the chip.
8 FILT output PLL loop filter output; an RC network must be connected between this pin and analog ground, with the ground end returned directly to AGND for minimum jitter.
9 RST input Reset input; when low the CS8416 enters a low-power mode with all internal states reset, and RST must be held low until supplies and input clocks are stable at power-up.
10 RXP4 input Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND.
11 RXP5 input Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND.
12 RXP6 input Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND.
13 RXP7 input Positive AES3/SPDIF input, part of the RXP[7:0] 8:2 S/PDIF input multiplexer; single-ended or differential, AC-coupled, with unused inputs left floating or tied to AGND.
14 AD0 / CS input Address bit 0 in I2C mode or control port chip select in SPI mode; a falling edge selects SPI mode, and with no falling edge the device defaults to I2C mode.
15 AD1 / CDIN input Address bit 1 in I2C mode or serial control data input in SPI mode.
16 SCL / CCLK input Control port clock (I2C SCL or SPI CCLK), used to clock control data in and out; it is an open-drain output requiring an external pull-up resistor to VL.
17 SDA / CDOUT bidirectional Serial control data I/O in I2C mode (open drain, requires external pull-up to VL) or control data output in SPI mode.
18 AD2 / GPO2 output General purpose output 2; when using I2C control port this pin must be pulled high or low through a 47 kOhm resistor to set the AD2 address bit.
19 GPO1 output General purpose output 1, source selected through GPO1SEL bits; all GPO pins default to GND after reset.
20 GPO0 output General purpose output 0, source selected through GPO0SEL bits; all GPO pins default to GND after reset.
21 VL power_in Logic power supply setting the I/O and receiver input levels, nominally +3.3 V or +5.0 V (3.13 V to 5.25 V range).
22 DGND power_in Digital and I/O ground for the I/O and core logic; AGND and DGND should be connected to a common ground area under the chip.
23 VD power_in Digital core power supply, nominally +3.3 V (3.13 V to 3.46 V range).
24 RMCK output Input section recovered master clock output, 256x Fs by default or 128x Fs when RMCKF is set; may be placed in high impedance by the RXD bit.
25 OMCK input System clock input; when OMCK System Clock Mode is enabled it is output on RMCK upon PLL unlock and serves as the OMCK/RMCK ratio reference.
26 SDOUT output Serial audio output data; in Software Mode this pin must be pulled high to VL through a 47 kOhm resistor to select Software Mode.
27 OSCLK bidirectional Serial audio output bit clock, an output in master mode and an input in slave mode, for data on SDOUT.
28 OLRCK bidirectional Serial audio output left/right word clock, an output at the sample rate Fs in master mode and an input in slave mode.

Key specifications

Parameter Value
Manufacturer Cirrus Logic
Package SOIC-28
Category Communication Interface Chip
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power Supply Voltage VA (analog) VA 3.13 3.3 3.46 V AGND, DGND = 0 V 6
Power Supply Voltage VD (digital core) VD 3.13 3.3 3.46 V AGND, DGND = 0 V 6
Power Supply Voltage VL (logic I/O) VL 3.13 5.25 V VL 3.3 V or 5.0 V option; typ printed as '3.3 or 5.0' 6
Ambient Operating Temperature, Commercial Grade TA -10 70 °C Commercial Grade 6
Power Supply Voltage VA, VD, VL (absolute max) VA, VD, VL 6 V 6
Input Current, Any Pin Except Supplies Iin -10 10 mA Note 1: transient currents up to 100 mA will not cause SCR latch-up 6
Input Voltage Vin -0.3 V 6
Ambient Operating Temperature (power applied) TA -55 125 °C Power applied 6
Storage Temperature Tstg -65 150 °C 6
Supply Current in Power-Down, VA IA 10 μA Power-Down Mode (Notes 2, 4) 7
Supply Current in Power-Down, VD ID 70 μA Power-Down Mode (Notes 2, 4) 7
Supply Current in Power-Down, VL IL 10 μA Power-Down Mode (Notes 2, 4); VL = 3.3 V 7
Supply Current in Power-Down, VL IL 12 μA Power-Down Mode (Notes 2, 4); VL = 5.0 V 7
Supply Current at 48 kHz Frame Rate, VA IA 5.7 mA Normal Operation (Notes 3, 4) 7
Supply Current at 48 kHz Frame Rate, VD ID 5.9 mA Normal Operation (Notes 3, 4) 7
Supply Current at 48 kHz Frame Rate, VL IL 2.8 mA Normal Operation (Notes 3, 4); VL = 3.3 V 7
Supply Current at 48 kHz Frame Rate, VL IL 4.2 mA Normal Operation (Notes 3, 4); VL = 5.0 V 7
Supply Current at 192 kHz Frame Rate, VA IA 9.4 mA Normal Operation (Notes 3, 4) 7
Supply Current at 192 kHz Frame Rate, VD ID 23 mA Normal Operation (Notes 3, 4) 7
Supply Current at 192 kHz Frame Rate, VL IL 7.8 mA Normal Operation (Notes 3, 4); VL = 3.3 V 7
Supply Current at 192 kHz Frame Rate, VL IL 11.8 mA Normal Operation (Notes 3, 4); VL = 5.0 V 7
Input Leakage Current IIN -0.5 0.5 μA 7
Differential Input Sensitivity, RXP[7:0] to RXN VTH 150 200 mVpp RXP[7:0] to RXN 7
Input Hysteresis VH 0.15 1 V 7
Low-Level Output Voltage VOL 0.5 V IOL = 3.2 mA 7
High-Level Input Voltage, except RXP[7:0], RXN VIH 2 V except RXP[7:0], RXN 7
Low-Level Input Voltage, except RXP[7:0], RXN VIL -0.3 0.8 V except RXP[7:0], RXN 7
RST Pin Low Pulse Width 200 μS CL = 20 pF 8
PLL Clock Recovery Sample Rate Range 30 200 kHz 8
RMCK Output Duty-Cycle 45 50 55 % Note 6: clock recovered from biphase encoded input 8
RMCK Output Duty-Cycle 50 55 65 % Note 7: OMCK switched over for output on RMCK 8
RMCK/OMCK Maximum Frequency 50 MHz 8
RMCK Output Jitter 200 ps RMS Note 5: typical RMS cycle-to-cycle jitter 8
OSCLK/OLRCK Active Edge to SDOUT Output Valid tdpd 23 ns Note 8 9
RMCK to OSCLK Active Edge Delay, Master Mode tsmd 0 12 ns Master Mode; Note 8 9
RMCK to OLRCK Delay, Master Mode tlmd 0 12 ns Master Mode; Note 9 9
OSCLK Period, Slave Mode tsckw 36 ns Slave Mode 9
OSCLK Input Low Width, Slave Mode tsckl 14 ns Slave Mode 9
OSCLK Input High Width, Slave Mode tsckh 14 ns Slave Mode 9
OSCLK Active Edge to OLRCK Edge, Slave Mode tlrckd 10 ns Slave Mode; Notes 8, 9, 10 9
OSCLK Edge Setup Before OSCLK Active Edge, Slave Mode tlrcks 10 ns Slave Mode; Notes 8, 9, 11 9
CCLK Clock Frequency fsck 0 6 MHz Note 12 10
CS High Time Between Transmissions tcsh 1 µs SPI Mode 10
CS Falling to CCLK Edge tcss 20 ns SPI Mode 10
CCLK Low Time tscl 66 ns SPI Mode 10
CCLK High Time tsch 66 ns SPI Mode 10
CDIN to CCLK Rising Setup Time tdsu 40 ns SPI Mode 10
CCLK Rising to DATA Hold Time tdh 15 ns SPI Mode; Note 13 10
CCLK Falling to CDOUT Stable tpd 50 ns SPI Mode 10
Rise Time of CCLK and CDIN tr2 100 ns Note 14: for fsck < 1 MHz 10
SCL Clock Frequency fscl 100 kHz I2C Format 11
Bus Free Time Between Transmissions tbuf 4.7 µs I2C Format 11
Start Condition Hold Time thdst 4 µs Prior to first clock pulse 11
Clock Low Time tlow 4.7 µs I2C Format 11
Clock High Time thigh 4 µs I2C Format 11
Setup Time for Repeated Start Condition tsust 4.7 µs I2C Format 11
SDA Hold Time from SCL Falling thdd 10 ns Note 15 11
SDA Setup Time to SCL Rising tsud 250 ns I2C Format 11
Rise Time of SCL and SDA tr 1000 ns I2C Format 11
Setup Time for Stop Condition tsusp 4.7 µs I2C Format 11

CAD (KiCad official)

  • Symbol: CS8416-CSZR
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28 (KiCad packages3D, STEP)
  • 3D model files: cs8416-cszr-etched.step / cs8416-cszr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs8416-cszr.step / cs8416-cszr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cirrus Logic datasheet (60 pp, sha256 85bb158d11c6e9bf, retrieved 2026-11-13, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF