CS817x20HS

{
  "slug": "cs817x20hs",
  "version": "0.1.0",
  "type": "component",
  "description": "Chipanalog Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "signal isolation devices",
    "cs817x20hs",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cs817x20hs.kicad_sym",
    "cs817x20hs.kicad_mod",
    "cs817x20hs.glb",
    "cs817x20hs.step",
    "cs817x20hs.lbr",
    "docs/hero.png",
    "docs/cs817x20hs-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cs817x20hs-hero.glb",
    "cs817x20hs-hero.overlay.json",
    "cs817x20hs-etched.glb"
  ],
  "component": {
    "mpn": "CS817x20HS",
    "manufacturer": "Chipanalog",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Signal Isolation Devices",
    "subcategory": "Digital Isolators",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603003927482671104",
    "parts": {
      "symbol": "cs817x20hs.kicad_sym",
      "footprint": "cs817x20hs.kicad_mod",
      "model_3d": "cs817x20hs-hero.glb",
      "model_3d_plain": "cs817x20hs-etched.glb",
      "model_3d_step": "cs817x20hs-etched.step",
      "model_3d_step_plain": "cs817x20hs.step",
      "lbr": "cs817x20hs.lbr"
    },
    "distributor_links": {
      "lcsc": "C7422573"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T13:53:20Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD1",
        "type": "power_in",
        "description": "Power supply for side 1, operating from 2.375 V to 5.5 V and to be bypassed with at least 1 µF low-ESR ceramic capacitor to GND1."
      },
      {
        "number": "2",
        "name": "INA",
        "type": "input",
        "description": "Digital input A on side 1 (corresponds to output OUTA on side 2); logic thresholds are 0.7×VDDI1 (rising) and 0.3×VDDI (falling), with input voltage limited to -0.5 V to VDDI+0.5 V."
      },
      {
        "number": "3",
        "name": "INB",
        "type": "input",
        "description": "Digital input B on side 1 (corresponds to output OUTB on side 2); logic thresholds are 0.7×VDDI1 (rising) and 0.3×VDDI (falling), with input voltage limited to -0.5 V to VDDI+0.5 V."
      },
      {
        "number": "4",
        "name": "GND1",
        "type": "power_in",
        "description": "Ground reference for side 1, the isolated ground for the side 1 supply and inputs."
      },
      {
        "number": "5",
        "name": "GND2",
        "type": "power_in",
        "description": "Ground reference for side 2, the isolated ground for the side 2 supply and outputs, which must not be connected to GND1 as this defeats the isolation."
      },
      {
        "number": "6",
        "name": "OUTB",
        "type": "output",
        "description": "Digital output B on side 2, the logic output for input INB on side 1; the default state is high for HS devices when the input is unpowered or open."
      },
      {
        "number": "7",
        "name": "OUTA",
        "type": "output",
        "description": "Digital output A on side 2, the logic output for input INA on side 1; the default state is high for HS devices when the input is unpowered or open."
      },
      {
        "number": "8",
        "name": "VDD2",
        "type": "power_in",
        "description": "Power supply for side 2, operating from 2.375 V to 5.5 V and to be bypassed with at least 1 µF low-ESR ceramic capacitor to GND2."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Table 6-1 lists two pin numbers per signal (CS817x20 first, CS817x22 second) and the extracted layou; The datasheet labels INA/OUTA/INB/OUTB as 'Logic I/O' because the CS817x22 variant reverses directio; The datasheet does not state a value for the GND2 pin beyond being the side 2 ground reference; the "
        ],
        "pages_sent": 20,
        "cost_usd": 0.0944,
        "at": "2026-10-18T13:53:00"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603003927482671104",
        "pages": 20,
        "sha256": "370cfd8ae67fb372",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
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        "role": "eda",
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        "zmin_mm": -0.0,
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        "sha256": "4bf448dd245dd8fab2df8f1e831544261b3bc3e3fb4a4301ee1cf133f01ead79",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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  }
}